A silicon-controlled rectifier (SCR) includes a first-type field, a second-type first field and a second-type second field disconnectedly formed in a first-type well; an entire first-type doped region formed within the first-type field; a segmented second-type doped region formed within the second-type first field; and a segmented first-type doped region formed within the second-type second field.

Apparatus and methods for reducing minority carriers in a memory array are described herein. Minority carriers diffuse between ON cells and OFF cells, causing disturbances during write operation as well as reducing the retention lifetime of the cells. Minority Carrier Lifetime Killer (MCLK) region architectures are described for vertical thyristor memory arrays with insulation trenches. These MCLK regions encourage recombination of minority carriers. In particular, MCLK regions formed by conductors embedded along the cathode line of a thyristor array, as well as dopant MCLK regions are described, as well as methods for manufacturing thyristor memory cells with MCLK regions.

Methods and systems for reducing electrical disturb effects between thyristor memory cells in a memory array are provided. Electrical disturb effects between cells are reduced by using a material having a reduced minority carrier lifetime as a cathode line that is embedded within the array. Disturb effects are also reduced by forming a potential well within a cathode line, or a one-sided potential barrier in a cathode line.

A split electrode vertical cavity optical device includes an n-type ohmic contact layer, first through fifth ion implant regions, cathode and anode electrodes, first and second injector terminals, and p and n type modulation doped quantum well structures. The cathode electrode and the first and second ion implant regions are formed on the n-type ohmic contact layer. The third ion implant region is formed on the first ion implant region and contacts the p-type modulation doped QW structure. The fourth ion implant region encompasses the n-type modulation doped QW structure. The first and second injector terminals are formed on the third and fourth ion implant regions, respectively. The fifth ion implant region is formed above the n-type modulation doped QW structure and the anode electrode is formed above the fifth ion implant region.

A semiconductor device includes an n-type ohmic contact layer, cathode and anode electrodes, p-type and n-type modulation doped quantum well (QW) structures, and first and second ion implant regions. The anode electrode is formed on the first ion implant region that contacts the p-type modulation doped QW structure and the cathode electrode is formed by patterning the first and second ion implant regions and the n-type ohmic contact layer. The semiconductor device is configured to operate as at least one of a diode laser and a diode detector. As the diode laser, the semiconductor device emits photons. As the diode detector, the semiconductor device receives an input optical light and generates a photocurrent.

A semiconductor device is provided. On one main surface side of an n-type semiconductor substrate, a p-type diffusion region to serve as an anode of a diode is formed. A guard ring formed of a p-type diffusion region is formed to surround the anode. On the other main surface side, an n-type ultrahigh-concentration impurity layer and an n-type high-concentration impurity layer to serve as a cathode are formed. In a guard-ring opposed region located in the cathode and opposite to the guard ring, a cathode-side p-type diffusion region is formed. Accordingly, concentration of the electric current on an outer peripheral end portion of the anode is suppressed.

A die stack assembly includes first and second power semiconductor device dice. The first die has a P type peripheral edge separation structure that extends from the top planar semiconductor surface of the first die all the way to the bottom planar semiconductor surface of the die, and that is doped at least in part with aluminum. The backside of the first die is mounted to the backside of the second die. A metal feature that is not covered with passivation, and that can serve as a bonding pad, is disposed on part of the peripheral edge separation structure. A metal member (for example, a bond wire or metal clip) contacts the metal feature such that an electrical connection is established from the metal member, through the metal feature, through the peripheral edge separation structure of the first die, and to an electrode of the second die.

Methods and systems include constructing and operating a semiconductor device with a mid-band dopant layer. In various implementations, carriers that are optically excited in a mid-band dopant region may provide injection currents that may reduce transition times and increase achievable operating frequency in a bipolar junction transistor (BJT). In various implementations, carriers that are optically excited in a mid-band dopant region within a thyristor may improve closure transition time, effective current spreading velocity, and maximum rate of current rise.

A Dual-wavelength hybrid (DWH) device includes an n-type ohmic contact layer, cathode and anode terminal electrodes, first and second injector terminal electrodes, p-type and n-type modulation doped QW structures, and first through sixth ion implant regions. The first injector terminal electrode is formed on the third ion implant region that contacts the p-type modulation doped QW structure and the second injector terminal electrode is formed on the fourth ion implant region that contacts the n-type modulation doped QW structure. The DWH device operates in at least one of a vertical cavity mode and a whispering gallery mode. In the vertical cavity mode, the DWH device converts an in-plane optical mode signal to a vertical optical mode signal, whereas in the whispering gallery mode the DWH device converts a vertical optical mode signal to an in-plane optical mode signal.

A manufacturable and economically viable edge termination structure allows a semiconductor device to withstand a very high reverse blocking voltage (for example, 8500 volts) without suffering breakdown. A P type peripheral aluminum diffusion region extends around the bottom periphery of a thick die. The peripheral aluminum diffusion region extends upward from the bottom surface of the die, extending into N type bulk silicon. A deep peripheral trench extends around the upper periphery of the die. The deep trench extends from the topside of the die down toward the peripheral aluminum diffusion region. A P type sidewall doped region extends laterally inward from the inner sidewall of the trench, and extends laterally outward from the outer sidewall of the trench. The P type sidewall doped region joins with the P type peripheral aluminum diffusion region, thereby forming a separation edge diffusion structure that surrounds the active area of the die.