A semiconductor structure and manufacturing method thereof are provided. The semiconductor structure includes a metallization structure with a top surface. A conductive pad is over the top surface. An upper passivation layer is over the top surface and the conductive pad and includes a first implanted region. A polymer layer is over the upper passivation layer and the conductive pad. A conductive via penetrates through the upper passivation layer and the polymer layer, and electrically coupled to the conductive pad. A method for manufacturing a semiconductor structure is also provided.

The disclosure provides a small photoelectric sensor that can secure a capacity for accommodating optical components and secure sealing properties. The small photoelectric sensor includes a holder in which an opening, an edge that defines the opening, and four fixing parts that are independently provided at four corners of a front surface are formed on the front surface; a cover lens that is provided at a position interposed between the four fixing parts, and is connected to the edge in a region overlapping the edge; and an optical component that is held by the holder and projects or receives light through the opening.

Embodiments of the present disclosure are directed towards techniques and configurations to provide solder contacts for electrical connection in socket assemblies. In one embodiment, a solder contact may be disposed on the bottom surface of a die package such that the solder contact is conductively coupled to electrical contacts of the die package. The solder contacts may be disposed to be coupled to pins of a socket assembly, to provide conductive coupling of the electrical contacts of the die package and the pins of the socket assembly. The solder may be selected to be sufficiently soft to provide for better electrical conduction. The pins may also be configured to penetrate the solder contact to provide for better electrical conduction. Other embodiments may be described and/or claimed.

When a power semiconductor device is energized, heat generated from upper-side power semiconductor chips mounted on a P-potential electrode transfers to a first heat mass portion and a second heat mass portion, and heat generated from lower-side power semiconductor chips mounted on a intermediate potential electrode transfers to a resistor. A lead frame, the power semiconductor chip, an inner lead and the resistor are placed in symmetry with respect to a centerline, which can reduce the difference among the temperature increases of the power semiconductor chips when energized. In this way, transient temperature increase of the power semiconductor chip can be suppressed without adding a new member, such as a heat diffusion plate.

Embodiments of the present disclosure are directed towards techniques and configurations to provide solder contacts for electrical connection in socket assemblies. In one embodiment, a solder contact may be disposed on the bottom surface of a die package such that the solder contact is conductively coupled to electrical contacts of the die package. The solder contacts may be disposed to be coupled to pins of a socket assembly, to provide conductive coupling of the electrical contacts of the die package and the pins of the socket assembly. The solder may be selected to be sufficiently soft to provide for better electrical conduction. The pins may also be configured to penetrate the solder contact to provide for better electrical conduction. Other embodiments may be described and/or claimed.

Embodiments of the present disclosure are directed towards techniques and configurations to provide solder contacts for electrical connection in socket assemblies. In one embodiment, a solder contact may be disposed on the bottom surface of a die package such that the solder contact is conductively coupled to electrical contacts of the die package. The solder contacts may be disposed to be coupled to pins of a socket assembly, to provide conductive coupling of the electrical contacts of the die package and the pins of the socket assembly. The solder may be selected to be sufficiently soft to provide for better electrical conduction. The pins may also be configured to penetrate the solder contact to provide for better electrical conduction. Other embodiments may be described and/or claimed.

A semiconductor structure includes an encapsulated die including an electronic die and an insulating layer laterally covering the electronic die, and a photonic die coupled to the encapsulated die. The photonic die includes an optical device in proximity to an edge coupling facet of the photonic die. In a top-down view, a boundary of the electronic die is within a boundary of the insulating layer, and the boundary of the insulating layer is within a boundary of the photonic die.

A semiconductor structure includes an encapsulated die and a photonic die coupled to the encapsulated die. The photonic die includes a first portion and a second portion connected to the first portion, the first portion includes a first sidewall coterminous with a sidewall of the encapsulated die and an optical device disposed in proximity to the first sidewall, and the second portion includes a second sidewall laterally offset from the first sidewall of the first portion.

An example apparatus includes: an integrated circuit including a first surface and terminals; a package including: a housing around the integrated circuit, the housing exposing the first surface; and an electrical interconnect including a second surface and an opening, the second surface electrically coupled to the terminals, the second surface mechanically coupled to the housing, the opening configured to expose the first surface.