A fault detecting multi-thread pipeline processor with fault detection is operative with a single pipeline stage which generates branch status comprising at least one of branch taken/not_taken, branch direction, and branch target. A first thread has control and data instructions, the control instructions comprising loop instructions including unconditional and conditional branch instructions, loop initialization instructions, loop arithmetic instructions, and no operation (NOP) instructions. A second thread has only control instructions and either has the non-control instructions replaced with NOP instructions, or removed entirely. A fault detector compares the branch status of the first thread and second thread and asserts a fault output when they do not match.

A method for configuring a computer system memory, includes powering on the computer system; retrieving options for initializing the computer system; assigning to a first segment of the memory a first pre-defined setting; assigning to a second segment of the memory a second pre-defined setting; and booting the computer system.

The subject disclosure is directed towards components in different server clusters, e.g., comprising software components such as components of a distributed computing system. Components are available for use by distributed computing system applications, yet managed by the distributed computing system runtime such that only a single instance can be activated and exist within communicating (non-partitioned) clusters. Also described is recovery from a situation in which no longer partitioned clusters each have created the same component.

The subject disclosure is directed towards components in different server clusters, e.g., comprising software components such as components of a distributed computing system. Components are available for use by distributed computing system applications, yet managed by the distributed computing system runtime such that only a single instance can be activated and exist within communicating (non-partitioned) clusters. Also described is recovery from a situation in which no longer partitioned clusters each have created the same component.

Improved techniques for disaster recover within storage area networks are disclosed. Embodiments include replicating a LIF of a primary cluster on a secondary cluster. LIF configuration information is extracted from the primary cluster. A peer node from a secondary cluster is located. One or more ports are located on the located peer node that match a connectivity of the LIF from the primary cluster. One or more ports are identified based upon one or more filtering criteria to generate a candidate port list. A port from the candidate port list is selected based at least upon a load of the port. Other embodiments are described and claimed.

A method for controlling operation of a medical device in a medical system having a medical device, a communication device including a remote control for the medical device, and a safety device adapted for data communication with the communication device. Input data is provided and processed by a first calculation to thereby provide a first calculation result. The input data is processed by a second calculation executed separately from first calculation to thereby provide a second calculation result. The first and second calculation results are compared. When the first and second calculation results are found equal, remote control of the medical device by a medical device application running on the communication device is allowed. When the first and second calculation results are found not equal, the medical device application running on the communication device for remote control of the medical device is prevented.

A method for managing a host memory buffer, a memory storage apparatus, and a memory control circuit unit are provided. The method includes: detecting whether a system abnormality occurs; copying a first command and first data corresponding to the first command stored in a data buffer of a host system to the memory storage apparatus in response to determining that the system abnormality occurs; executing an initial operation after copying the first command and the first data, wherein the initial operation initializes a part of a hardware circuit in the memory storage apparatus and does not initialize another part of the hardware circuit in the memory storage apparatus; and re-executing the first command stored in the memory storage apparatus after initializing the part of the hardware circuit.

An apparatus for controlling an operation in a memory system includes a volatile memory including plural memory cells, a column data checking circuitry configured to determine whether all pieces of data outputted from memory cells corresponding to a bit line are identical to each other, and an error correction circuitry configured to determine whether the pieces of data include an error based at least on a type of data, a state of data, and an output of the column data checking circuitry, and to resolve the error.

A solid state drive having a drive aggregator and a plurality of component solid state drive, including a first component solid state drive and a second component solid state drive. The drive aggregator has at least one host interface, and a plurality of drive interfaces connected to the plurality of component solid state drives. The drive aggregator is configured to generate, in the second solid state drive, a copy of a dataset that is stored in the first component solid state drive. In response to a failure of the first component solid state drive, the drive aggregator is configured to substitute a function of the first component solid state drive with respect to the dataset with a corresponding function of the second component solid state drive, based on the copy of the dataset generated in the second component solid state drive.

A method for accessing a memory module includes; encoding first data of a first partial burst length to generate first parities and first cyclic redundancy codes, encoding second data of a second partial burst length to generate second parities and second cyclic redundancy codes, writing the first data and the second data to first memory devices, and writing the first parities, the first cyclic redundancy codes, the second parities, and the second cyclic redundancy codes to a second memory device and a third memory device.