A semiconductor device which shifts a low-level signal is provided. In an example, a first transistor including a first terminal electrically connected to a first wiring and a second terminal electrically connected to a second wiring, a second transistor including a first terminal electrically connected to a third wiring and a second terminal electrically connected to the second wiring, a third transistor including a first terminal electrically connected to a fourth wiring and a second terminal electrically connected to a gate of the second transistor, a fourth transistor including a first terminal electrically connected to a fifth wiring, a second terminal electrically connected to a gate of the third transistor, and a gate electrically connected to a sixth wiring, and a first switch including a first terminal electrically connected to the third wiring and a second terminal electrically connected to a gate of the first transistor are included.

The present invention provides a liquid crystal display that can reduce occurrence of quality problems and improve adhesive strength between substrates. The present invention is a liquid crystal display including a first substrate, a second substrate, and a seal. The first substrate includes a shift register monolithically formed on an insulating substrate, a plurality of bus lines, a first end, and a display region. The shift register includes a plurality of multistage-connected unit circuits and wiring connected to the plurality of unit circuits, and is arranged in a region between the first end and the display region. At least one of the unit circuits includes a clock terminal, an output terminal, an output transistor, a second transistor, and a bootstrap capacitor. The output transistor and the bootstrap capacitor are arranged in a region between the first end and one of the wiring and the second transistor.

A scan line to which a selection signal or a non-selection signal is input from its end, and a transistor in which a clock signal is input to a gate, the non-selection signal is input to a source, and a drain is connected to the scan line are provided. A signal input to the end of the scan line is switched from the selection signal to the non-selection signal at the same or substantially the same time as the transistor is turned on. The non-selection signal is input not only from one end but also from both ends of the scan line. This makes it possible to inhibit the potentials of portions in the scan line from being changed at different times.

A display panel and a display drive method thereof, and a display device are provided. The display panel includes a plurality of display regions and a plurality of scan drive circuits, the plurality of display regions includes a first display region and a second display region that are parallel to each other and do not overlap with each other, and the plurality of scan drive circuits includes a first scan drive circuit and a second scan drive circuit, the first and second display regions are connected to the first and second scan drive circuits to respectively receive a first light-emitting control signal, and the display drive method includes: individually adjusting a pulse width of at least one of the first light-emitting control signal and the second light-emitting control signal to adjust the light-emitting durations of light-emitting elements of the first and second display regions within one display period, respectively.

The present disclosure relates to a static random-access memory and an electronic device. The memory includes at least one storage circuit, wherein the storage circuit includes a first inverter, a second inverter, a first switch, a second switch, a third switch, a fourth switch, a fifth switch, a word-line, a first bit-line, a second bit-line, a shift-input line, and a shift-output line. The circuit is used to access data by using the first bit-line and/or the second bit-line when it works in a first mode, and the circuit is used to shift the input data to the shift-input line and output the shifted data through the shift-output line when it works in a second mode. By implementing shift-input and shift-output within the memory, the disclosed embodiment can achieve high-concurrency data access and data update, and it also enables high integration and low power consumption.

A display substrate, a display panel and a display device. A pixel circuit includes a power supply wire providing a power supply voltage to the display pixel; a drive circuit in the non-display region includes a drive signal wire providing a drive signal to the pixel circuit; the power supply wire includes a narrow wire portion overlapping with the drive signal wire and a wide wire portion; a wire width of the narrow wire portion is less than that of the wide wire portion; the display substrate has a first side for display and a second side opposite to the first side, includes a bending region at an edge of the base substrate; the power supply wire and the drive signal wire extend from the first side to the bending region, crossing the bending region to extend to the second side; the narrow wire portion is on the second side.

An object is to provide a semiconductor device which can suppress characteristic deterioration in each transistor without destabilizing operation. In a non-selection period, a transistor is turned on at regular intervals, so that a power supply potential is supplied to an output terminal of a shift register circuit. A power supply potential is supplied to the output terminal of the shift register circuit through the transistor. Since the transistor is not always on in a non-selection period, a shift of the threshold voltage of the transistor is suppressed. In addition, a power supply potential is supplied to the output terminal of the shift register circuit through the transistor at regular intervals. Therefore, the shift register circuit can suppress noise which is generated in the output terminal.

A first flipflop outputs a first signal synchronized with a first clock signal, a second flipflop outputs a second signal synchronized with a second clock signal, and a third flipflop outputs a third signal synchronized with a third clock signal. The second flipflop includes first to fifth transistors. In the first transistor, the second clock signal is input to a first terminal and the second signal is output from a second terminal. In the second transistor, a first signal is input to a first terminal, a second terminal is electrically connected to a gate of the first transistor, and the first clock signal is input to a gate. In the third transistor, the third signal is input to a first terminal, a second terminal is electrically connected to the gate of the first transistor, and the third clock signal is input to a gate.

A shift-register unit circuit (100) includes a first input sub-circuit (120) configured to receive a display-input signal from a display-input terminal (STU2, VDD, VGH) and input a display output-control signal to a first node (Q) based on the display-input signal during a display period of one cycle of displaying one frame of image. The shift-register unit circuit (100) also includes a second input sub-circuit (110) configured to receive a blank-input signal for charging a blank-control node (H), and configured to input a blank-output-control signal to the first node (Q) based on the blank-input signal during a blank period of the one cycle. The shift-register unit circuit (100) further includes an output sub-circuit (130) configured to output a hybrid signal controlled by the first node (Q). The second input sub-circuit (110) is also configured, before an end of the blank period, to receive a first blank-reset signal to reset the blank-control node (H).

An integrated circuit for transition fault testing comprises a synchronizing circuit including a first set of shift registers coupled to receive a scan enable signal and to provide a synchronizing signal based on the scan enable signal; a clock leaker circuit coupled to the synchronizing circuit and including a second set of shift registers coupled to receive a first clock signal based on the synchronizing signal and to provide a second clock signal that includes a set of pulses; and a multiplexer (MUX) that includes a first input coupled to receive a shift clock, a second input coupled to the clock leaker circuit to receive the second clock signal, and an output configured to provide an output clock signal that includes a second set of pulses.