A system for filtering measurement data, comprising: a bus adapter, configured to obtain a data source from an Electronic Control Unit (ECU); at least one computer device, comprising a processor, a display communicating with the processor to present a graphical interface, a readable storage medium, a communication bus and communication interface; wherein, the processor, the readable storage medium and the communication interface communicate with the bus adapter via the communication bus; the readable storage medium is configured to store instructions; the processor is configured to, after obtaining the data source, execute the instructions to perform the operations: setting an upstream data flow input port, a downstream data flow output port and a filtering function for each measurement window; connecting the upstream data flow input port of each measurement window to the downstream data flow output port of one measurement window other than the measurement window to form a hierarchical connection.

Methods, apparatus, systems, and articles of manufacture are disclosed to debug a hardware accelerator such as a neural network accelerator for executing Artificial Intelligence computational workloads. An example apparatus includes a core with a core input and a core output to execute executable code based on a machine-learning model to generate a data output based on a data input, and debug circuitry coupled to the core. The debug circuitry is configured to detect a breakpoint associated with the machine-learning model, compile executable code based on at least one of the machine-learning model or the breakpoint. In response to the triggering of the breakpoint, the debug circuitry is to stop the execution of the executable code and output data such as the data input, data output and the breakpoint for debugging the hardware accelerator.

A server system includes a first control circuit and a second control circuit. The first control circuit includes a first controller, a second controller, a first input/output circuit, and a second input/output circuit. The first input/output circuit is coupled to the first controller. The second input/output circuit is coupled to the second controller and the first input/output circuit. The second controller is configured to transmit a debug log of the first control circuit to the second input/output circuit. The second input/output circuit is configured to transmit the debug log of the first control circuit to the first input/output circuit. The second control circuit is coupled between the first input/output circuit and the second input/output circuit. The second control circuit is configured to selectively control data to be transmitted from the first input/output circuit to the second input/output circuit.

Integrated circuits may include registers that store register states. Only a subset of the registers may store critical register states. The subset of registers may be specially demarcated, such as using synthesis directions in the hardware description, and may be coupled to dedicated extraction/loading circuitry. The extraction/loading circuitry may be implemented using soft or hard logic or can leverage existing programming or debugging circuitry on a programmable integrated circuit. The extraction/loading mechanism may also be implemented using multiplexers and associated control circuitry, scan chain circuitry, a memory-mapped interface, a tool-instantiated or user-instantiated finite state machine, or external memory interface logic. Accessing critical register states in this way can help improve efficiency with live migration events, debugging, retiming, and other integrated circuit operations.

A data processing apparatus is provided that includes storage circuitry for storing a data value derived from a plurality of memory addresses associated with a stream of instructions. Membership query circuitry performs an approximate set membership query against the data value of a memory address associated with a current one of the instructions and in response to the approximate set membership query being positive, issues the memory address to confirmation circuitry. Halt circuitry halts execution of the stream of instructions by processing circuitry in response to at least one condition being met, the at least one condition including a positive indication from the confirmation circuitry that the memory address is one of the plurality of memory addresses.

Methods, apparatus, systems, and articles of manufacture are disclosed to debug a hardware accelerator such as a neural network accelerator for executing Artificial Intelligence computational workloads. An example apparatus includes a core with a core input and a core output to execute executable code based on a machine-learning model to generate a data output based on a data input, and debug circuitry coupled to the core. The debug circuitry is configured to detect a breakpoint associated with the machine-learning model, compile executable code based on at least one of the machine-learning model or the breakpoint. In response to the triggering of the breakpoint, the debug circuitry is to stop the execution of the executable code and output data such as the data input, data output and the breakpoint for debugging the hardware accelerator.

This application is directed to communicating telemetry and debugging data of a memory system using optical signals. An enclosed memory device has an optical indicator and receives a data request. In response to the data request, the enclosed memory device obtains internal activity data stored in the memory device, encodes the internal activity data into an electrical signal, and drives the optical indicator with the electrical signal to generate a visible light signal carrying the internal activity data. In some embodiments, the enclosed memory device includes a solid-state drive. In some embodiments, the internal activity data includes telemetry data stored by the enclosed memory device while the memory device is processing a sequence of memory access requests including at least one of a read request and a write request.

A system for filtering measurement data includes: a bus adapter, configured to obtain a data source from an Electronic Control Unit (ECU); at least one computer device, including a processor, a display communicating with the processor to present a graphical interface, a readable storage medium, a communication bus and communication interface; where the processor, the readable storage medium and the communication interface communicate with the bus adapter via the communication bus; the readable storage medium is configured to store instructions; the processor is configured to, after obtaining the data source, execute the instructions to perform the operations: setting an upstream data flow input port, a downstream data flow output port and a filtering function for each measurement window; connecting the upstream data flow input port of each measurement window to the downstream data flow output port of one measurement window other than the measurement window to form a hierarchical connection.

Methods, systems, and devices for error detection event mechanism are described. The memory system may identify a fault condition and transmit, to a host system, a message indicating a first indication that the fault condition exists at the memory system. In some cases, the memory system may set, in a register of the memory system, a second indication indicating a type of the fault condition based on identifying the fault condition. The memory system may perform a recovery procedure based on the first indication and the second indication.

A method for use in a computing device, the method comprising: transmitting, to a context manager, a context request associated with a process that is executed in a virtual machine; receiving, from the context manager, a context identifier in response to the context request; transmitting, to an introspection Application Programming Interface (API), a memory access request that is based, at least in part, on the context identifier.