Radio frequency (RF) generators are disclosed. A RF generator may include an analog signal generator configured to generate a pulsed analog signal responsive to a digital pulsed waveform defined by one or more commands. The RF generator may also include a modulator configured to generate a pulsed radio frequency (RF) signal by modulating an RF carrier using the pulsed analog signal as a modulating signal. Further, the RF generator may include an amplification stage configured to amplify the pulsed RF signal output by the modulator. RF generation systems and methods of generating a pulsed RF signal also disclosed.

Radio frequency (RF) generators are disclosed. A RF generator may include an analog signal generator configured to generate a pulsed analog signal responsive to a digital pulsed waveform defined by one or more commands. The RF generator may also include a modulator configured to generate a pulsed radio frequency (RF) signal by modulating an RF carrier using the pulsed analog signal as a modulating signal. Further, the RF generator may include an amplification stage configured to amplify the pulsed RF signal output by the modulator. RF generation systems and methods of generating a pulsed RF signal also disclosed.

An example apparatus includes a circuit and calibration circuitry. The circuit has complementary input ports to receive input signals including a monotonously rising and/or falling wave reference signal and a voltage-test signal to test at least one direct current (DC) voltage associated with the circuit by comparing the input signals using a first polarity and second polarity associated with the circuit to produce a first output signal and a second output signal. During operation, the circuit manifests an input voltage offset and a signal delay with each comparison of the input signals. The calibration circuitry processes the first and second output signals and, in response, calibrates or sets an adjustment for at least one signal path associated with the circuit in order to account for the input offset voltage and signal delay during normal operation of the circuit.

An example apparatus includes a circuit and calibration circuitry. The circuit has complementary input ports to receive input signals including a monotonously rising and/or falling wave reference signal and a voltage-test signal to test at least one direct current (DC) voltage associated with the circuit by comparing the input signals using a first polarity and second polarity associated with the circuit to produce a first output signal and a second output signal. During operation, the circuit manifests an input voltage offset and a signal delay with each comparison of the input signals. The calibration circuitry processes the first and second output signals and, in response, calibrates or sets an adjustment for at least one signal path associated with the circuit in order to account for the input offset voltage and signal delay during normal operation of the circuit.

The detection matrix for an Orthogonal Differential Vector Signaling code is typically embodied as a transistor circuit with multiple active signal inputs. An alternative detection matrix approach uses passive resistor networks to sum at least some of the input terms before active detection.

The detection matrix for an Orthogonal Differential Vector Signaling code is typically embodied as a transistor circuit with multiple active signal inputs. An alternative detection matrix approach uses passive resistor networks to sum at least some of the input terms before active detection.

In an example, a circuit includes a first comparator, a second comparator, a pulse counter, a processor, a first ADC, and a second ADC. The first comparator has a first input coupled to a first node, a second input, and an output. The second comparator has a first input coupled to a second node, a second input, and an output. A first DAC is coupled to the second input of the first comparator. A second DAC is coupled to the second input of the second comparator. The pulse counter has a first input coupled to the output of the first comparator and a second input coupled to the output of the second comparator. The first ADC has an input coupled to the first node and an output coupled to the processor. The second ADC has an input coupled to the second node and an output coupled to the processor.

In an example, a circuit includes a first comparator, a second comparator, a pulse counter, a processor, a first ADC, and a second ADC. The first comparator has a first input coupled to a first node, a second input, and an output. The second comparator has a first input coupled to a second node, a second input, and an output. A first DAC is coupled to the second input of the first comparator. A second DAC is coupled to the second input of the second comparator. The pulse counter has a first input coupled to the output of the first comparator and a second input coupled to the output of the second comparator. The first ADC has an input coupled to the first node and an output coupled to the processor. The second ADC has an input coupled to the second node and an output coupled to the processor.

An external audio device includes a USB (Universal Serial Bus) plug, an audio socket, a USB communication circuit, an audio socket detection circuit, a first power circuit, a second power circuit, and a control circuit. The USB communication circuit establishes a connection with a computer device coupled to the USB plug according to the communication protocol of USB. The audio socket detection circuit detects a plug-in state of the audio socket. The first power circuit generates a second power to the USB communication circuit according to a first power received from the USB plug. The second power circuit generates a third power to the audio socket detection circuit according to the first power. The control circuit enables or disables the first power circuit according to the plug-in state of the audio socket.

Disclosed is a system comprising a plurality of operational amplifiers, each operational amplifier having individually adjustable operational parameters, and a trimming circuit. The trimming circuit includes successive approximation register (SAR) logic that determines associated memory values. The trimming circuit changes the adjustable operational parameters of each operation amplifier based on the associated memory values.