Mixed-signal circuitry including a set of capacitive digital-to-analogue converter, CDAC, units for carrying out digital-to-analogue conversion operations to convert respective digital values into corresponding analogue values; and control circuitry, where: each CDAC unit includes an array of capacitors at least some of which are configured to be individually-switched dependent on the digital values, the capacitors configured to have nominal capacitances; a given capacitor of the array of capacitors in each of the CDAC units is a target capacitor; the set of CDAC units includes a plurality of sub-sets of CDAC units; at least one of the target capacitors per sub-set of CDAC units is a variable capacitor, controllable by the control circuitry to have any one of a plurality of nominal capacitances defined by the configuration of that capacitor.

Aspects relate to a photonic processing system, an integrated circuit, and a method of operating an integrated circuit to control components to modulate optical signals. A photonic processing system, comprising: a photonic integrated circuit comprising: a first electrically-controllable photonic component electrically coupling an input pin to a first output pin; and a second electrically-controllable photonic component electrically coupling the input pin to a second output pin.

Transceiver circuitry in an integrated circuit device includes a receive path including an analog front end for receiving analog signals from an analog transmission path and conditioning the analog signals, and an analog-to-digital converter configured to convert the conditioned analog signals into received digital signals for delivery to functional circuitry, and a transmit path including a digital front end configured to accept digital signals from the functional circuitry and to condition the accepted digital signals, and a digital-to-analog converter configured to convert the conditioned digital signals into analog signals for transmission onto the analog transmission path. At least one of the analog front end and the digital front end introduces distortion and outputs a distorted conditioned signal. The transceiver circuitry further includes distortion correction circuitry at the one of the analog front end and the digital front end, to determine and apply a distortion cancellation function to the distorted signal.

A control circuit and a method of calibrating a signal converter (such as DAC) are disclosed. The control circuit can be an existing control circuit, so no additional calibration circuit is required and the circuit area can be reduced. The control circuit can be an embedded microcontroller or other type of microcontroller. In general, the microcontroller includes an analog comparator and an arithmetic unit. With the combination of using the arithmetic unit to execute firmware program codes and using of the analog comparator, the control circuit is able to calibrate the signal converter.

The present disclosure provides a mixer circuit, a transmitter, and a communication device. The mixer circuit comprises an I-channel digital-to-analog converter, a Q-channel digital-to-analog converter, a low-pass filter, and a passive quadrature mixer, wherein the low-pass filter comprises an active device, so that an output admittance of the mixer circuit contains conductance dependent of frequency. The consistency between the gains of the mixer circuit at the upper sideband and the lower sideband can be improved.

The present disclosure provides a mixer circuit, a transmitter, and a communication device. The mixer circuit comprises an I-channel digital-to-analog converter, a Q-channel digital-to-analog converter, a low-pass filter, and a passive quadrature mixer, wherein the low-pass filter comprises an active device, so that an output admittance of the mixer circuit contains conductance dependent of frequency. The consistency between the gains of the mixer circuit at the upper sideband and the lower sideband can be improved.

A dynamic element matching (DEM) encoder is provided that converts an N-bit digital codeword into a pattern of 1-bit values. The DEM encoder includes a binary switching tree that includes plurality of switching blocks interconnected between an encoder input and a plurality of encoder outputs. The plurality of switching blocks are configured to receive a plurality of first control signals such that each switching block receives a respective first control signal and is independently programmable based on the respective first control signal into a first mode or a second mode. Each switching block includes a splitting circuit programmed into the first mode or the second mode to split a digital input into two digital outputs using either both a first splitting operation and a second splitting operation that is different from the first splitting operation or the first splitting operation over the plurality of sampling intervals.

Disclosed are devices, systems and methods for accelerating vector-based computation. In one example aspect, an accelerator apparatus includes a plurality of mixed-signal units, each of which includes a first digital-to-analog convertor configured to convert a subset of digital-domain bits to a first analog-domain signal and a second digital-to-analog convertor configured to convert a subset of digital-domain bits to a second analog-domain signal. Each mixed-signal unit also includes a capacitor coupled to the digital-to-analog convertors to accumulate a result of a multiplication operation as an analog signal. The apparatus includes a circuitry coupled to the mixed-signal units to shift part of the analog signals of the plurality of mixed-signal units. The circuitry comprises an additional capacitor to store an analog-domain result for a multiply-accumulate operation. The apparatus also includes an analog-to-digital converter coupled to the circuitry to convert the analog-domain result into a digital-domain result.

Techniques regarding error detection in one or more generated signals based on one or more signal-to-noise ratios are provided. For example, one or more embodiments described herein can include a system, which can include a memory that can store computer executable components. The system can also include a processor, operably coupled to the memory, and that can execute the computer executable components stored in the memory. The computer executable components can include a signal analysis component that can determine a signal-to-noise ratio associated with a generated signal, wherein the signal-to-noise ratio incorporates a signal value based on a reference signal and a noise value based on a difference between the reference signal and an acquired signal.

Certain aspects of the present disclosure provide a digital-to-analog conversion circuit. The digital-to-analog conversion circuit generally includes a detection circuit configured to detect digital transitions in a digital input signal. The digital-to-analog conversion circuit also includes a clock-gating circuit having an input coupled to an output of the detection circuit. The clock-gating circuit is configured to gate a clock signal for the digital-to-analog conversion circuit based on an output signal from the detection circuit.