A combined I/Q DAC is provided with a plurality of sources corresponding to a plurality of selectors in which the corresponding source drives the corresponding selector with a source signal to produce a corresponding pair of in-phase and quadrature-phase analog input signals to a summation network. Each selector routes its source signal responsive to a digital value of a corresponding in-phase and quadrature-phase bit pair.

Embodiments disclosed herein may reduce or even eliminate spurs introduced into the signals during analog to digital or digital to analog conversions. The spurs may be introduced by components such as clocks of the converter circuits. In an analog to digital conversion, the input signal may be split into two parts: the first portion passing through a first analog to digital converter (ADC) and an inverted second portion passing through a second ADC. A digital subtractor may subtract the output of the second ADC from the output of the first ADC converter thereby reducing the spurs. In digital to analog conversion, a digital input is passed through a first digital to analog converter (DAC) and an inverted digital input is passed through a second DAC. The output of the second DAC is inverted and combined with the output of the first DAC to reduce the spurs.

A circuit system for weight modulation and image recognition of a memristor array includes a personal computer (PC), a field-programmable gate array (FPGA) chip, a digital-to-analog conversion unit, a switch unit, a memristor array unit, an integration and signal amplification circuit, and an analog-to-digital converter. The circuit system selects a to-be-realized function such as array reading and writing, weight modulation or image recognition, converts a command or an RGB value of an image collected by the PC into a corresponding grayscale value, and sends the grayscale value to the FPGA chip. The FPGA chip controls and selects a to-be-modulated memristor array unit through the digital-to-analog conversion unit and the switch unit. An application program of the PC controls the FPGA chip in real time to realize array reading and writing, weight modulation, and image recognition, and then the FPGA chip displays a result on the PC in real time.

A circuit system for weight modulation and image recognition of a memristor array includes a personal computer (PC), a field-programmable gate array (FPGA) chip, a digital-to-analog conversion unit, a switch unit, a memristor array unit, an integration and signal amplification circuit, and an analog-to-digital converter. The circuit system selects a to-be-realized function such as array reading and writing, weight modulation or image recognition, converts a command or an RGB value of an image collected by the PC into a corresponding grayscale value, and sends the grayscale value to the FPGA chip. The FPGA chip controls and selects a to-be-modulated memristor array unit through the digital-to-analog conversion unit and the switch unit. An application program of the PC controls the FPGA chip in real time to realize array reading and writing, weight modulation, and image recognition, and then the FPGA chip displays a result on the PC in real time.

A digital-to-analog converter is provided. The digital-to-analog converter comprises a delay circuit configured to iteratively delay a digital input signal based on a clock signal for generating a plurality of delayed digital input signals. Further, the digital-to-analog converter comprises a plurality of groups of inverter cells. Each group of inverter cells is configured to generate a respective analog signal based on one of the plurality of delayed digital input signals. The inverter cells comprise a respective inverter circuit configured to invert the respective delayed digital input signal. The plurality of groups of inverter cells comprise different numbers of inverter cells. The digital-to-analog converter additionally comprises an output configured to output an analog output signal based on the analog signals of the plurality of groups of inverter cells.

A digital to analog converter is constructed using a neural network layer. The converter has inputs for receiving parallel bits of a digital input signal and an output for outputting an analog signal which is based on the digital input. Connecting the input and the output is a neural network layer which is configured to convert the parallel bits into an output analog signal that is representative of the digital input signal. The neural network may be hardwired and the synapses may rely on memristors as programmable elements.

The present invention discloses a DAC method having signal calibration mechanism is provided. Operation states of current sources are controlled to generate an output analog signal by a DAC circuit according to a codeword of an input digital signal. An echo signal is generated by an echo transmission circuit according to the output analog signal. The codeword is mapped to generate an offset signal by a calibration circuit according to a codeword offset mapping table. The offset signal is processed to generate an echo-canceling signal by an echo-canceling circuit. By a calibration parameter calculation circuit, offset amounts are generated according to a difference between the echo signal and the echo-canceling signal, the offset amounts are grouped to perform statistic operation according to the operation states and current offset values are calculated according to calculation among groups and converted to codeword offset values to update the codeword offset mapping table.

The present invention discloses a DAC method having signal calibration mechanism is provided. Operation states of current sources are controlled to generate an output analog signal by a DAC circuit according to a codeword of an input digital signal. An echo signal is generated by an echo transmission circuit according to the output analog signal. The codeword is mapped to generate an offset signal by a calibration circuit according to a codeword offset mapping table. The offset signal is processed to generate an echo-canceling signal by an echo-canceling circuit. By a calibration parameter calculation circuit, offset amounts are generated according to a difference between the echo signal and the echo-canceling signal, the offset amounts are grouped to perform statistic operation according to the operation states and current offset values are calculated according to calculation among groups and converted to codeword offset values to update the codeword offset mapping table.

Described are apparatus and methods to calibrate and align multiple high-speed clock domains. A system includes at least two clock domains, a launch circuit connected to each of the at least two domains, and a calibration circuit. Each clock domain including a resettable device having a local reset retime clock. The launch circuit aligns a reset pulse with the local reset retime clock by using a launch clock from one of the domains, where the reset pulse is incoherent with respect to the domains, adjusts a delay of the launch clock to control a launch time of the reset pulse, and sends the reset pulse based on the delayed launch clock. The calibration circuit samples a local reset retime delayed clock to generate a readback signal. The launch circuit and the calibration circuit iterate through selected delays until safe arrival timing is indicated from each readout.

This application discloses a clock synchronization system, including a quantum control processor (QCP) and N digital/analog mutual conversion devices, each digital/analog mutual conversion device including a frequency conversion module and a signal synchronization module that includes a D flip-flop (DFF). The QCP generates a global synchronization signal and reference clock signals; and transmits the global synchronization signal and a reference clock signal to the frequency conversion module and transmits the global synchronization signal to the signal synchronization module of each conversion device. The frequency conversion module performs frequency conversion processing on the reference clock signal to obtain a target clock signal, and generates a signal synchronization instruction according to the global synchronization signal; and transmits the signal synchronization instruction and the target clock signal to the signal synchronization module. The signal synchronization module performs, based on the global synchronization signal, signal synchronization on the target clock signal through the DFF.