An analog to digital conversion (ADC) circuit includes a voltage-controlled oscillator (VCO)-based quantizer that receives a voltage input signal to be quantized and provides a digital output. A predictor samples the digital output, evaluates correlation between successive samples, and predicts a predicted input sample from the correlation to minimize voltage-to-frequency transfer of the VCO. A feedback loop L1 with a digital to analog converter (DAC) receives the predicted input sample, converts it and subtracts it from the voltage input signal. A feedback loop L2 adds the predicted sample to the digital output.

Techniques are described to address P-MOS bias temperature instability (BTI) stress issues within capacitive radio frequency digital-to-analog converter (CDAC) using a circuit architecture solution that functions to protect the transistors in various operating conditions. Techniques are disclosed that function to float one or both of the negative and positive power supply rail voltages higher or lower, respectively, for CDAC cells depending upon various operating scenarios. These scenarios include the transmitting state of individual CDAC cells and the transmitting state of the CDAC array in which the CDAC cell is implemented.

Techniques are described to address P-MOS bias temperature instability (BTI) stress issues within capacitive radio frequency digital-to-analog converter (CDAC) using a circuit architecture solution that functions to protect the transistors in various operating conditions. Techniques are disclosed that function to float one or both of the negative and positive power supply rail voltages higher or lower, respectively, for CDAC cells depending upon various operating scenarios. These scenarios include the transmitting state of individual CDAC cells and the transmitting state of the CDAC array in which the CDAC cell is implemented.

A method for a multichannel geophysical data acquisition system is provided in the field of electrical resistivity tomography. Individual and autonomous node operating systems are provided. Separate communication channels for upstream and downstream data transfer, high voltage transfer and synchronization signals are provided. A novel use of high voltage isolation barriers is also provided. A direct memory access data transfer process is provided.

Certain aspects of the present disclosure are directed to a radio frequency digital-to-analog converter (RFDAC). The RFDAC generally includes a plurality of digital-to-analog (DAC) unit cells. At least one DAC unit cell is capable of being configured in an active state or in a sleep state. For the at least one DAC unit cell, an output impedance of the DAC unit cell in the active state is equal to an output impedance of the DAC unit cell in the sleep state.

Certain aspects of the present disclosure are directed to a radio frequency digital-to-analog converter (RFDAC). The RFDAC generally includes a plurality of digital-to-analog (DAC) unit cells. At least one DAC unit cell is capable of being configured in an active state or in a sleep state. For the at least one DAC unit cell, an output impedance of the DAC unit cell in the active state is equal to an output impedance of the DAC unit cell in the sleep state.

A digital-analog converter of the disclosure converts digital image data to generate analog data signals. The digital-analog converter includes a voltage divider which generates a plurality of gamma reference voltages based on a first reference voltage and a second reference voltage; a global ramp including a plurality of gamma decoders which generates a plurality of global gamma voltages based on the gamma reference voltages; a decoder which selects one of the global gamma voltages according to the digital image data to generate the analog data signals; and a ramp controller which turns off at least some of the gamma decoders based on the digital image data.

A digital-analog converter of the disclosure converts digital image data to generate analog data signals. The digital-analog converter includes a voltage divider which generates a plurality of gamma reference voltages based on a first reference voltage and a second reference voltage; a global ramp including a plurality of gamma decoders which generates a plurality of global gamma voltages based on the gamma reference voltages; a decoder which selects one of the global gamma voltages according to the digital image data to generate the analog data signals; and a ramp controller which turns off at least some of the gamma decoders based on the digital image data.

A quantum circuit generator for a quantum computer includes a controller; and a plurality of analog conversion units (ACUs) operatively connected to the controller, each ACU being operatively connected to a corresponding qubit of a plurality of qubits, wherein each ACU is configured to convert a digital input from the controller into an analog input at a microwave frequency to control a quantum state of the corresponding qubit. The controller is configured to generate a quantum circuit using at least two qubits of the plurality of qubits, the at least two qubits being selected by the controller based on corresponding classical bits being mapped by the controller and based on latency of the generated quantum circuit so that the generated quantum circuit has a latency less than a threshold latency.

Methods and apparatus for dynamically controlling a quantum computer are described wherein the method includes selecting a first and second digital pulse signal stored in a memory, the first digital pulse signal having a first pulse shape and a first sample rate and the second digital pulse signal having a second pulse shape and a second sample rate, at least the first or the second sample rate being lower than an output sampling rate of a digital-to-analog converter (DAC); forming a digital pulse sequence signal, the forming including applying a first interpolation algorithm to determine a first upsampled digital pulse signal based on the first digital signal and a second interpolation algorithm to determine a second upsampled digital pulse signal based on the second digital signal, the sample rates of the first and second upsampled digital signals matching the sample rate of the DAC; and, providing the digital pulse sequence signal comprising the first and second upsampled digital pulse signals to an input of the DAC to transform the first and second upsampled digital signals into an analog pulse sequence signal for controlling the quantum device.