The present disclosure relates to a solid state image sensor and an electronic apparatus capable of performing a gain transition at high speed. A ramp generation circuit includes sample hold circuits and ramp generation DACs, the number of which depends on kinds of required gains (for example, two kinds, i.e. a low gain and a high gain). Then, the two sample hold circuits can individually hold gain DAC output voltages at the different gains. This enables a switch to the ramp generation DAC holding the required gain voltage by means of a ramp selection signal. The present disclosure can be applied, for example, to a CMOS solid state image sensor that is used for an imaging device.

The present disclosure relates to a solid state image sensor and an electronic apparatus capable of performing a gain transition at high speed. A ramp generation circuit includes sample hold circuits and ramp generation DACs, the number of which depends on kinds of required gains (for example, two kinds, i.e. a low gain and a high gain). Then, the two sample hold circuits can individually hold gain DAC output voltages at the different gains. This enables a switch to the ramp generation DAC holding the required gain voltage by means of a ramp selection signal. The present disclosure can be applied, for example, to a CMOS solid state image sensor that is used for an imaging device.

An exponential scale pulse width modulation (PWM) controller comprises a waveform generator circuit configured to generate a logarithmic waveform signal that has the shape of an increasing logarithm function; and a first comparator circuit including a first input to receive the logarithmic waveform signal, a second input to receive an input signal, and an output that provides a PWM control signal that includes signal pulses having a duty cycle that changes exponentially with respect to the input signal.

A digital-to-analog converter and a digital-to-analog conversion method thereof are provided. The digital-to-analog conversion method includes: converting a digital data signal into an analog data signal in a first cycle according to a clock signal, resetting the analog data signal in a second cycle according to the clock signal and a reset signal corresponding to a first reset level, and compensating for a voltage level of the reset analog data signal in the second cycle according to a second reset level, so that the voltage level of the reset analog data signal is the second reset level. The second reset level is higher or lower than the first reset level.

A bandgap voltage reference circuit includes first and second transistors (e.g., 3-terminal BJTs or diode-connected BJTs), and a PTAT element (e.g., resistance or capacitance). The first transistor is at a first die location, and operates with a first base-emitter voltage. The second transistor is at a second die location, and operates with a second base-emitter voltage. Each of the first and second transistors may include multiple individual parallel-connected transistors. The PTAT element is operatively coupled to the first and second transistors such that a voltage difference between the first and second base-emitter voltages drops across the PTAT element. The first and second locations are separated by a distance (e.g., 1.5% or more of die length, or such that the respective centroids of the first and second transistor are spaced from one another). Such spatial distribution helps mitigate voltage shift induced by mechanical stress, and is insensitive to process variation.

A circuit system includes an analog-to-digital converter circuit, a digital-to-analog converter circuit coupled to the analog-to-digital converter circuit, and a variable latency circuit coupled to a data path that includes the digital-to-analog converter circuit. The variable latency circuit generates a deterministic latency in an output signal that is based on a measured latency of the data path.

An isolation amplifier of an embodiment includes: a primary circuit including an encoder configured to encode an input signal and output the encoded input signal and an anomaly detection circuit configured to detect anomaly having occurred to the input signal and generate a detection signal; an isolation unit configured to insulate the primary circuit from a secondary circuit; an output circuit configured to generate an output signal corresponding to the input signal; and an anomaly-input sensing-output circuit configured to generate an output signal from the secondary circuit by changing the output signal from the output circuit based on the detection signal.

An analog video signal supply circuit includes a processing circuit that supplies first and second digital video signals. First and second digital-to-analog converters convert digital signals to analog signals. A control circuit controls operation in a first configuration where the first digital video signal is applied to an input of the first digital-to-analog converter and the second digital video signal to an input of the second digital-to-analog converter. The control circuit further controls operation in a second configuration where the first digital video signal is simultaneously applied to the inputs of the first and second digital-to-analog converters.

An analog video signal supply circuit includes a processing circuit that supplies first and second digital video signals. First and second digital-to-analog converters convert digital signals to analog signals. A control circuit controls operation in a first configuration where the first digital video signal is applied to an input of the first digital-to-analog converter and the second digital video signal to an input of the second digital-to-analog converter. The control circuit further controls operation in a second configuration where the first digital video signal is simultaneously applied to the inputs of the first and second digital-to-analog converters.

Novel and useful quantum structures having a continuous well with control gates that control a local depletion region to form quantum dots. Local depleted well tunneling is used to control quantum operations to implement quantum computing circuits. Qubits are realized by modulating gate potential to control tunneling through local depleted region between two or more sections of the well. Complex structures with a higher number of qdots per continuous well and a larger number of wells are fabricated. Both planar and 3D FinFET semiconductor processes are used to build well to gate and well to well tunneling quantum structures. Combining a number of elementary quantum structure, a quantum computing machine is realized. An interface device provides an interface between classic circuitry and quantum circuitry by permitting tunneling of a single quantum particle from the classic side to the quantum side of the device. Detection interface devices detect the presence or absence of a particle destructively or nondestructively.