A transceiver includes a medium dependent interface configured to provide AC (alternate current) coupling between a first node and a second node; a broadband matching network 120 configured to couple the second node to a third node; a programmable gain amplifier configured to receive a third voltage signal at the third node and output a fourth voltage signal in accordance with a first logical signal; an analog-to-digital converter configured to receive the fourth voltage signal and output a first data in accordance with the first logical signal and a first clock; and a digital-to-analog converter configured to receive a second data and output a first current signal to the third node in accordance with a second logical signal and a second clock, wherein: the first logical signal and the second logical signal are asserted alternately.

A transceiver includes a medium dependent interface configured to provide AC (alternate current) coupling between a first node and a second node; a broadband matching network 120 configured to couple the second node to a third node; a programmable gain amplifier configured to receive a third voltage signal at the third node and output a fourth voltage signal in accordance with a first logical signal; an analog-to-digital converter configured to receive the fourth voltage signal and output a first data in accordance with the first logical signal and a first clock; and a digital-to-analog converter configured to receive a second data and output a first current signal to the third node in accordance with a second logical signal and a second clock, wherein: the first logical signal and the second logical signal are asserted alternately.

Systems, apparatuses, and methods for performing hybrid non-linearity correction for a digital-to-analog converter (DAC) are described. A circuit includes two correction LUTs, an edge-trim DAC, and a DAC core. A lookup of a first correction LUT is performed using a portion of the most significant bits (MSBs) of a received digital input value. A first correction value, retrieved from the first correction LUT, is applied to the digital input value to generate a corrected value. The corrected value is provided to the DAC core and to a second correction LUT. A second correction value, retrieved from the second correction LUT, is compared to the first correction value. If the second correction value is different from the first correction value, the difference is provided to the edge-trim DAC to generate an analog correction which is applied to an analog output of the DAC core.

A digital to analog converter for fiber optic gyroscope is disclosed. The digital to analog converter for fiber optic gyroscope includes a random unit generating a random number signal, a plurality of encoding units coupled with the random unit, a plurality of control units respectively one to one coupled with the plurality of encoding units, a current source array coupled with the plurality of control units, and an output load electrically connected to the current source array. Each of the plurality of encoding units converts a plurality of digital signals to a plurality of spin signals according to the random number signal. Each of the plurality of control units converts the plurality of spin signals to a plurality of logic signals. The current source array generates a total current according to the plurality of logic signals. The total current passes through the output load and forms an analog signal.

A digital to analog converter for fiber optic gyroscope is disclosed. The digital to analog converter for fiber optic gyroscope includes a random unit generating a random number signal, a plurality of encoding units coupled with the random unit, a plurality of control units respectively one to one coupled with the plurality of encoding units, a current source array coupled with the plurality of control units, and an output load electrically connected to the current source array. Each of the plurality of encoding units converts a plurality of digital signals to a plurality of spin signals according to the random number signal. Each of the plurality of control units converts the plurality of spin signals to a plurality of logic signals. The current source array generates a total current according to the plurality of logic signals. The total current passes through the output load and forms an analog signal.

The disclosure belongs to the field of integrated circuits, and is used for reducing an area overhead and a power consumption of a pipelined analog-to-digital converter. Each stage of the pipelined analog-to-digital converter according to the disclosure comprises an analogue-to-digital converter, a digital-to-analog converter, a subtractor and an amplifier. According to the disclosure, an amplification time of the pipelined ADC is used for extra quantization, and a number of bits of each ADC is reduced on the premise of not increasing a number of stages of the pipelined ADC, so that a scale of each circuit is greatly reduced, and the power consumption and the area overhead are reduced.

Systems and methods for facilitating intercom communication for one or more quick-service restaurant drive-throughs are disclosed. Exemplary implementations may: capture sound from a customer placing an order; generate order information signals that represent the captured sound; encode signals to form order data packets; transmit the order data packets to a base station through a single pair of wires that is also used to provide power; decode information from the order data packets; and generate order sound based on the decoded information, such that the generated order sound is audible to a staff member of the quick service restaurant through a headset.

Systems and methods for facilitating intercom communication for one or more quick-service restaurant drive-throughs are disclosed. Exemplary implementations may: capture sound from a customer placing an order; generate order information signals that represent the captured sound; encode signals to form order data packets; transmit the order data packets to a base station through a single pair of wires that is also used to provide power; decode information from the order data packets; and generate order sound based on the decoded information, such that the generated order sound is audible to a staff member of the quick service restaurant through a headset.

A Digital-to-Analog Converter (DAC) is provided. The DAC includes a code converter circuit configured to sequentially receive first digital control codes for controlling N digital-to-analog converter cells. N is an integer greater than one. The code converter circuit is further configured to convert the first digital control codes to second digital control codes. Additionally, the DAC includes a bit-shifter circuit configured to receive shift codes for the second digital control codes. The shift codes are obtained using dynamic element matching and indicate a respective circular shift by r.sub.i bit positions for the i-th second digital control code, wherein r.sub.i is an integer smaller than N−1. The bit-shifter circuit is further configured to generate third digital control codes by circularly shifting the second digital codes based on the shift codes. In addition, the DAC includes a cell activation circuit configured to selectively activate one or more of the N digital-to-analog converter cells based on the third digital control codes.

A test method is provided to test a semiconductor integrated circuit including an analog-to-digital converter and/or a digital-to-analog converter. An analog test signal having a test pattern is generated using an analog test signal generator or a digital test signal having the test pattern using a digital test signal generator. An analog output signal corresponding to the test pattern is generated by applying, as a digital input signal, the digital test signal having the test pattern to a digital-to-analog converter responsive to generation of the digital test signal. A digital output signal corresponding to the test pattern is generated by applying, as an analog input signal, the analog test signal having the test pattern or the analog output signal corresponding to the test pattern to an analog-to-digital converter. A normality of the semiconductor integrated circuit is determined based on the digital output signal corresponding to the test pattern.