Quantum repeater systems and apparatus for quantum communication. In one aspect, a system includes a quantum signal receiver configured to receive a quantum field signal; a quantum signal converter configured to: sample quantum analog signals from a quantum field signal received by the quantum signal receiver; encode sampled quantum analog signals as corresponding digital quantum information in one or more qudits, comprising applying a hybrid analog-digital encoding operation to each quantum analog signal and a qudit in an initial state; decode digital quantum information stored in the one or more qudits as a recovered quantum field signal, comprising applying a hybrid digital-analog decoding operation to each qudit and a quantum analog register in an initial state; a quantum memory comprising qudits and configured to store digital quantum information encoded by the quantum signal converter; and a quantum signal transmitter configured to transmit the recovered quantum field signal.

Quantum repeater systems and apparatus for quantum communication. In one aspect, a system includes a quantum signal receiver configured to receive a quantum field signal; a quantum signal converter configured to: sample quantum analog signals from a quantum field signal received by the quantum signal receiver; encode sampled quantum analog signals as corresponding digital quantum information in one or more qudits, comprising applying a hybrid analog-digital encoding operation to each quantum analog signal and a qudit in an initial state; decode digital quantum information stored in the one or more qudits as a recovered quantum field signal, comprising applying a hybrid digital-analog decoding operation to each qudit and a quantum analog register in an initial state; a quantum memory comprising qudits and configured to store digital quantum information encoded by the quantum signal converter; and a quantum signal transmitter configured to transmit the recovered quantum field signal.

A digital-to-analog conversion device and method are provided. The control module is configured to split the input digital signal into n intermediate digital portions, divide the n intermediate digital portions by the corresponding conversion coefficients to obtain n intermediate digital signals and transmit the n intermediate digital signals to the n conversion modules. The n intermediate digital portions increase progressively. The conversion module is configured to perform digital-to-analog conversion on an intermediate digital signal to obtain a result including the conversion coefficient of the conversion module. The adder is configured to add output signals of the n conversion modules to obtain an analog signal. The feedback module is configured to obtain a feedback signal according to the analog signal. The control module is further configured to adjust the allocation of the n intermediate digital portions according to a target digital signal and the feedback signal.

A digital-to-analog conversion circuit includes a first digital-to-analog converter (DAC) and a second DAC. The first DAC includes a first current generation circuit (CGC) and a first current-to-voltage converter. The first CGC generates a first current based on a first digital code received through a first terminal to provide the first current to an output node. The second DAC includes a second CGC and a second current-to-voltage converter. The second CGC generates a second current based on a second digital code received through a second input terminal to provide the second current to the output node. The first current-to-voltage converter and the second current-to-voltage converter convert a sum of the first current and the second current to a an analog voltage corresponding to a sum of the first digital code and the second digital code, and output the analog voltage at the output node.

A digital-to-analog conversion circuit includes a first digital-to-analog converter (DAC) and a second DAC. The first DAC includes a first current generation circuit (CGC) and a first current-to-voltage converter. The first CGC generates a first current based on a first digital code received through a first terminal to provide the first current to an output node. The second DAC includes a second CGC and a second current-to-voltage converter. The second CGC generates a second current based on a second digital code received through a second input terminal to provide the second current to the output node. The first current-to-voltage converter and the second current-to-voltage converter convert a sum of the first current and the second current to a an analog voltage corresponding to a sum of the first digital code and the second digital code, and output the analog voltage at the output node.

A test method is provided to test a semiconductor integrated circuit including an analog-to-digital converter and/or a digital-to-analog converter. An analog test signal having a test pattern is generated using an analog test signal generator or a digital test signal having the test pattern using a digital test signal generator. An analog output signal corresponding to the test pattern is generated by applying, as a digital input signal, the digital test signal having the test pattern to a digital-to-analog converter responsive to generation of the digital test signal. A digital output signal corresponding to the test pattern is generated by applying, as an analog input signal, the analog test signal having the test pattern or the analog output signal corresponding to the test pattern to an analog-to-digital converter. A normality of the semiconductor integrated circuit is determined based on the digital output signal corresponding to the test pattern.

A method for mitigating interference across analog signal lines includes receiving a digital data stream including a plurality of discrete signal patterns configured to drive a plurality of different analog signal lines. An edge buffer for each analog signal line is populated with edge data representing pulse edges of upcoming signal patterns set to drive the analog signal line. A target buffer for a target signal line is populated with target data representing a target signal pattern. Edge buffers corresponding to potentially interfering analog signal lines are searched to identify potentially interfering pulse edges. A set of potentially interfering pulse edges are selected for interference mitigation, and the target signal pattern is modified to perform preemptive interference mitigation based at least in part on the selected pulse edges.

A method for mitigating interference across analog signal lines includes receiving a digital data stream including a plurality of discrete signal patterns configured to drive a plurality of different analog signal lines. An edge buffer for each analog signal line is populated with edge data representing pulse edges of upcoming signal patterns set to drive the analog signal line. A target buffer for a target signal line is populated with target data representing a target signal pattern. Edge buffers corresponding to potentially interfering analog signal lines are searched to identify potentially interfering pulse edges. A set of potentially interfering pulse edges are selected for interference mitigation, and the target signal pattern is modified to perform preemptive interference mitigation based at least in part on the selected pulse edges.

A microphone system includes: a microphone including a microphone output terminal and a microphone GND terminal, the microphone being configured to output, as an input sound signal, a voltage signal exhibiting a change in voltage between the microphone output terminal and the microphone GND terminal depending on an input sound; an A/D converting unit mounted on a first circuit board and configured to perform digital conversion on the input sound signal that is input; and a power supply circuit mounted on a second circuit board connected to the first circuit board via a pair of power supply lines, and configured to feed DC power to the A/D converting unit via the pair of power supply lines. The microphone outputs the input sound signal to the A/D converting unit via a pair of first signal lines different from the pair of power supply lines.

A microphone system includes: a microphone including a microphone output terminal and a microphone GND terminal, the microphone being configured to output, as an input sound signal, a voltage signal exhibiting a change in voltage between the microphone output terminal and the microphone GND terminal depending on an input sound; an A/D converting unit mounted on a first circuit board and configured to perform digital conversion on the input sound signal that is input; and a power supply circuit mounted on a second circuit board connected to the first circuit board via a pair of power supply lines, and configured to feed DC power to the A/D converting unit via the pair of power supply lines. The microphone outputs the input sound signal to the A/D converting unit via a pair of first signal lines different from the pair of power supply lines.