Methods of nonlinear differentiation and nonlinear differentiators are described. A log-sign nonlinear differentiator and an adaptive gain log-sign differentiator for signal tracking in a digital signal processor receive an input signal, u(t), estimates a filtered first state, x.sub.1(t) of the input signal, estimates second state signal, x.sub.2(t), and receive parameters which cause the filtered first state, x.sub.1(t), to converge asymptotically to the input signal, u(t), and the second state signal, x.sub.2(t), to converge asymptotically to the first derivative {dot over (u)}(t) of the input signal, u(t), such that a first output, y.sub.1(t), of the log-sign nonlinear differentiator, is an estimate of the input signal, u(t), and a second output, y.sub.2(t) equals the first derivative, {dot over (u)}(t) of the input signal, u(t), tracked by the log-sign nonlinear differentiator. The adaptive log-sign differentiator includes a signal path which includes calculating a deadzone function at the input of the first differentiator.

A multi-level signal generator includes a receiving circuit, a setting circuit, a data bit generating circuit and a digital-to-analog converter. The receiving circuit generates a first data bit based on an input data signal having two voltage levels that are different from each other. The setting circuit generates a flag signal based on a command signal. The flag signal is changed depending on an operation mode. The data bit generating circuit generates a plurality of internal bits based on the first data bit, selects at least one of the plurality of internal bits based on the flag signal, and outputs the selected internal bit as at least one additional data bit. The digital-to-analog converter generates an output data signal that is a multi-level signal having three or more voltage levels different from each other based on the first data bit and the at least one additional data bit.

Systems and methods are provided for a clock generator is configured to generate N clock signals evenly spaced by phase. A clock generator includes a poly phase filter configured to utilize a differential clock signal to generate N intermediate signals, the intermediate signals being spaced approximately 360/N degrees apart in phase. A phase error corrector is configured to receive the intermediate signals and to generate N clock output signals, where a phase error is a measure of a difference in phase between consecutive ones of the clock output signals from 360/N degrees, the phase error corrector being configured to reduce phase error among the clock output signals based on a feedback signal. A phase error detection circuit is configured to receive the clock output signals and to generate the feedback signal based on detected phase errors among the clock output signals.

Systems and methods are provided for a clock generator is configured to generate N clock signals evenly spaced by phase. A clock generator includes a poly phase filter configured to utilize a differential clock signal to generate N intermediate signals, the intermediate signals being spaced approximately 360/N degrees apart in phase. A phase error corrector is configured to receive the intermediate signals and to generate N clock output signals, where a phase error is a measure of a difference in phase between consecutive ones of the clock output signals from 360/N degrees, the phase error corrector being configured to reduce phase error among the clock output signals based on a feedback signal. A phase error detection circuit is configured to receive the clock output signals and to generate the feedback signal based on detected phase errors among the clock output signals.

A mixed-signal logic processor is provided. The mixed-signal logic processor includes a plurality of mixed-signal multiplier branches. Each of the plurality of mixed-signal multiplier branches has a set of branch-dedicated switches and a single branch-dedicated capacitor. The mixed-signal logic further includes a common switch. The common switch is external and common to each of the plurality of mixed-signal multiplier branches. The mixed-signal logic also includes a first shared branch-external capacitor and a second shared branch-external capacitor. The first and the second shared branch-external capacitors are external to and shared by each of the plurality of mixed-signal multiplier branches. Various settings of the set of switches and the common switch enable various modes of the mixed-signal dot product processor.

The present invention relates to a new type of current driving circuit, which has high linearity during low current driving, comprising: a voltage-current conversion unit for converting an input voltage into a current; a digital analog converter (DAC) connected to an output terminal of the voltage-current conversion unit and for generating and outputting a voltage corresponding to an applied digital code; a field effect transistor having a first electrode connected to a load and a second electrode connected to a node connected to a resistor, and for allowing a current to flow to the load in response to a voltage applied to a gate; an amplifier for receiving the voltage output from the digital analog converter and a voltage generated by the resistor, generating a voltage for controlling such that a current flows from the field effect transistor, and applying same to the gate; a current supply source for supplying to the first electrode a current required for operating the field effect transistor in a saturation region; and a control unit for controlling the field effect transistor to operate in the saturation region, by activating the current supply source, if the field effect transistor operates in a region lower than a threshold voltage.

The present invention relates to a new type of current driving circuit, which has high linearity during low current driving, comprising: a voltage-current conversion unit for converting an input voltage into a current; a digital analog converter (DAC) connected to an output terminal of the voltage-current conversion unit and for generating and outputting a voltage corresponding to an applied digital code; a field effect transistor having a first electrode connected to a load and a second electrode connected to a node connected to a resistor, and for allowing a current to flow to the load in response to a voltage applied to a gate; an amplifier for receiving the voltage output from the digital analog converter and a voltage generated by the resistor, generating a voltage for controlling such that a current flows from the field effect transistor, and applying same to the gate; a current supply source for supplying to the first electrode a current required for operating the field effect transistor in a saturation region; and a control unit for controlling the field effect transistor to operate in the saturation region, by activating the current supply source, if the field effect transistor operates in a region lower than a threshold voltage.

A filter circuit includes: a division unit that divides an input signal and adds, to a tail end of a division block, of head data of the next division block, to generate an input block; a plurality of signal processing units that perform filtering of a feedback type on input blocks to generate output samples, and generate and output blocks; and a coupling unit that couples the output blocks. The signal processing unit outputs first output samples generated until a switching timing, and outputs second output samples generated by the signal processing unit after the timing. The switching timing is a timing within a period corresponding to the duplicated data, at which timing a difference between a first signal generated by the signal processing unit and a second signal generated by the signal processing unit is less than or equal to a threshold consecutively for a second data length.

An apparatus is configured to generate, from a stream of periodic digital samples, a first sub-stream of periodic analog samples and a second sub-stream of periodic analog samples, each sub-stream comprising substantially stable time intervals. The apparatus is further configured to generate a sign-modulated sub-stream by applying to the second sub-stream a sign modulation operation effecting a sign transition during a stable time interval of the second sub-stream. The apparatus is further configured to generate an output stream of periodic analog samples based on a sum of the first sub-stream and the sign-modulated sub-stream, wherein a period of the output stream is shorter than periods of the first and second sub-streams.

Embodiments provide a pre-distortion circuit and apparatus, a method and computer program for pre-distorting, a transmitter, a radio transceiver, a communication device, a mobile transceiver, a base station transceiver and a storage. The pre-distortion circuit (10) is configured for a digital quadrature signal. The pre-distortion circuit (10) comprises a first input (12) for an inphase component of the quadrature signal and a second input (14) for a quadrature component of the quadrature signal. The pre-distortion circuit 10 comprises a signal processing circuit (16) configured to determine whether polarities of the inphase component and quadrature component are equal, and to determine pre-distortion coefficients based on the amplitude of the inphase component, the amplitude of the quadrature component, and based on whether the polarities are equal.