A transport framework for heterogeneous data streams includes session management module and a connection management module. The session management module is configured to receive a request to establish a first stream that is used for transmitting or receiving data, where the request includes an express indication as to whether the first stream is reliable or unreliable; construct a first data frame based on application data; handoff the first data frame to the connection management module; and maintain a record for the first data frame that includes whether the first data frame is successfully transmitted to the receiver. The connection management module is configured to receive the first data frame of the first stream from the session management module; receive a second frame from the session management module; encapsulate the first data frame and the second frame in a packet; and transmit the packet to the receiver using an unreliable protocol.

An apparatus for communication between a sending application and a receiving application of a receiving apparatus includes a processor that is configured to establish a stream for transmitting data between the sending application and the receiving application; receive a first request from the sending application to transmit metadata to the receiving application; receive a second request from the sending application to transmit application data to the receiving application; responsive to a determination that a frame that includes the application data and the metadata has a size that is smaller than or equal to a maximum frame size, construct the frame to include the application data and the metadata; and transmit the frame in a packet to the receiving apparatus.

Method and system for managing the reception of data frames, scheduled statically and periodically, a frame includes a header provided with an identifier (id) of the frame and an index (index) representing the occurrence of the frame in a hyper-period.

An example apparatus includes: a feed forward equalizer (FFE) with a FFE output, adder circuitry with a first adder input, a second adder input, and a first adder output, the first adder input coupled to the FFE output, a multiplexer (MUX) with a first MUX input, a second MUX input, and a MUX output, the first MUX input coupled to the first adder output, the second MUX input coupled to the FFE output, a decision feedback equalizer (DFE) with a DFE output coupled to the second adder input, and a timing error detector (TED) with a first TED input coupled to the MUX output.

An eye opening monitor device and an operation method thereof are provided. The eye opening monitor device includes a phase interpolator, a first sampling circuit, a second sampling circuit, and a clock centering circuit. The first sampling circuit samples a data signal according to a data clock to generate first sampled data. The second sampling circuit samples the data signal according to a phase interpolation clock to generate second sampled data. The phase interpolator changes a phase of the phase interpolation clock according to a phase interpolation code. The clock centering circuit counts multiple comparison results of the first sampled data and the second sampled data in multiple clock cycles to obtain an error count value for any one of different phase interpolation codes. The clock centering circuit determines the phase interpolation code provided to the phase interpolator based on the error count values corresponding to different phase interpolation codes.

A system includes a plurality of line cards and a timing card. A clock generation circuit on the timing card generates a clock signal which is pulse width modulated according to information to be transmitted. A clock line supplies the pulse width modulated clock signal to the line cards. The timing card sends a first control word to the plurality of line cards over the clock line after sending a beacon. The first control word includes a size field specifying a first length of first data following the first control word. The timing card sends time of day information over the clock line to the line cards following the first control word. The time of day information may be encrypted. A second control word follows the time of day information. One or more additional control words can follow the second control word before the next beacon.

Methods and systems are described for generating a time-varying information signal at an output of a continuous time linear equalizer (CTLE), asynchronously sampling a data signal according to a sampling clock having a frequency less than a data rate of the data signal; generating corresponding pattern-verified samples for at least two data patterns, each of the at least two data patterns having a respective frequency content; determining corresponding frequency-specific voltage measurements associated with each of the at least two data patterns based on the corresponding pattern-verified samples of the at least two data patterns; and adjusting an equalization of the data signal based on a comparison of the corresponding frequency-specific voltage measurements.

A computer-implemented method includes using a transmitter to send data from the transmitter through a plurality of lanes to a receiver using a synchronous operation mode that includes sending the data from the transmitter through the plurality of lanes to the receiver in a synchronous transmission manner that relies on an alignment between a transmitter clock frequency and a receiver clock frequency. A synchronous operation performance analysis (SOPA) is performed during the synchronous operation mode. A switch from the synchronous operation mode to an asynchronous operation mode is made based on a result of performing the SOPA. The asynchronous operation mode includes sending the data from the transmitter through the plurality of lanes to the receiver without requiring alignment between the transmitter clock frequency and the receiver clock frequency.

A hybrid receiver circuit included in a computer system may include both an analog and an ADC-based receiver circuit. A front-end circuit generates different equalized signals based on received signals that encode a serial data stream that includes multiple data symbols. Depending on a baud rate of the serial data stream, either the digital receive circuit or the analog receiver circuit is activated to provide the desired performance and power consumption over the range of possible baud rates. The ADC-based receiver circuit may include multiple analog-to-digital converter circuits with different resolutions that can be selected for different baud rates.

The present invention provides a receiver including a filter, a signal detection circuit and a synchronization processing circuit. The filter is configured to filter a filter input signal to generate a filter output signal. The signal detection circuit is configured to determine whether the filter input signal or the filter output signal includes an interference signal according to the filter input signal and the filter output signal, to generate an interference signal indicator; wherein when the interference signal indicator indicates that the filter input signal or the filter output signal includes the interference signal, the signal detection circuit further determines whether the filter output signal comprises an effective signal to generate an effective signal indicator. The synchronization processing circuit is configured to process the filter output signal according to the interference signal indicator and the effective signal indicator.