Methods and systems are provided for controlling wide LAG and ECMP in a network. At the ingress edge of the network, a switch can identify packets as LAG or ECMP packets, and allow them to be forwarded through the switch fabric using multiple output ports or paths.

Methods and systems are provided for controlling wide LAG and ECMP in a network. At the ingress edge of the network, a switch can identify packets as LAG or ECMP packets, and allow them to be forwarded through the switch fabric using multiple output ports or paths.

Memory requests are protected by encoding memory requests to include error correction codes. A subset of bits in a memory request are compared to a pre-defined pattern to determine whether the subset of bits matches a pre-defined pattern, where a match indicates that a compression can be applied to the memory request. The error correction code is generated for the memory request and the memory request is encoded to remove the subset of bits, add the error correction code, and add at least one metadata bit to the memory request to generate a protected version of the memory request, where the at least one metadata bit identifies whether the compression was applied to the memory request.

Memory requests are protected by encoding memory requests to include error correction codes. A subset of bits in a memory request are compared to a pre-defined pattern to determine whether the subset of bits matches a pre-defined pattern, where a match indicates that a compression can be applied to the memory request. The error correction code is generated for the memory request and the memory request is encoded to remove the subset of bits, add the error correction code, and add at least one metadata bit to the memory request to generate a protected version of the memory request, where the at least one metadata bit identifies whether the compression was applied to the memory request.

Systems and methods for dynamic buffer management in switches that facilitate a data-driven intelligent networking system are provided. The system can accommodate dynamic traffic with fast, effective congestion control while providing efficient use of internal input buffer space.

Systems and methods for dynamic buffer management in switches that facilitate a data-driven intelligent networking system are provided. The system can accommodate dynamic traffic with fast, effective congestion control while providing efficient use of internal input buffer space.

In an aspect, systems and methods of connected nodes, including electronic control units (ECUs) in a vehicle, integrate remote direct memory access (RDMA) capabilities with time-sensitive networking (TSN) traffic shaper configurations in a manner that guarantees lossless, bounded-latency critical traffic (CT) streams, while also allowing for different classes of traffic to flow through the connected nodes. In another aspect, mechanisms are introduced to enable an automotive software framework (e.g., classic AUTOSAR) to support RDMA communications.

A signal transfer device according to an embodiment receives a plurality of signals including an aperiodic signal having a higher priority than other signals, respectively holds the plurality of received signals by a plurality of buffers according to the priority, acquires signal information including at least one of a time at which the aperiodic signal is transmitted or received and a data length of the aperiodic signal, predicts a timing at which the aperiodic signal arrives at the buffer based on the acquired signal information, sets reservation of a period for transmitting the aperiodic signal with priority over other signals based on the predicted timing, controls the plurality of buffers to output the aperiodic signal with priority over other signals in the period in which the reservation is set, and transmits the signal output by the buffer.

A signal transfer device according to an embodiment receives a plurality of signals including an aperiodic signal having a higher priority than other signals, respectively holds the plurality of received signals by a plurality of buffers according to the priority, acquires signal information including at least one of a time at which the aperiodic signal is transmitted or received and a data length of the aperiodic signal, predicts a timing at which the aperiodic signal arrives at the buffer based on the acquired signal information, sets reservation of a period for transmitting the aperiodic signal with priority over other signals based on the predicted timing, controls the plurality of buffers to output the aperiodic signal with priority over other signals in the period in which the reservation is set, and transmits the signal output by the buffer.

A switch equipped with a reduction engine capable of being dynamically allocated in a network is provided. During operation, the reduction engine can be dynamically armed based on a multicast frame. As a result, the network can facilitate an efficient and scalable environment for high performance computing.