Circuit-Under-Pad (CUP) device topologies for high-current lateral power switching devices are disclosed, in which the interconnect structure and pad placement are configured for reduced source and common source inductance. In an example topology for a power semiconductor device comprising a lateral GaN HEMT, the source bus runs across a centre of the active area, substantially centered between first and second extremities of source finger electrodes, with laterally extending tabs contacting the underlying source finger electrodes. The drain bus is spaced from the source bus and comprises laterally extending tabs contacting the underlying drain finger electrodes. The gate bus is centrally placed and runs adjacent the source bus. Preferably, the interconnect structure comprises a dedicated gate return bus to separate the gate drive loop from the power loop. Proposed CUP device structures provide for lower source and common source inductance and/or higher current carrying capability per unit device area.

The invention concerns a field-effect transistor (100) having an interdigited structure and comprising: a plurality of elementary transistor cells (50) arranged in parallel, each elementary cell comprising a source electrode (1), a drain electrode (3), and a gate electrode (2) interposed between the source and drain electrodes, a source terminal (10) and a drain terminal (30) respectively connected to the source electrodes (1) and to the drain electrodes (3) of the elementary cells (50), a gate terminal (20) connected to the gate electrodes (2) of the elementary cells.

The field-effect transistor (100) only comprises vertical conductive vias to connect the gate electrodes to the gate terminal, and the gate terminal (20) is arranged vertically in line with all or part of the elementary cells (50).

A semiconductor module includes: a first metal plate including a first mount part joined with a bottom-surface electrode of a first switching element, a second mount part joined with a positive-electrode terminal, and a first narrow part between the first and second mount parts and being narrower than a part jointing the first switching element to the first mount part and the positive-electrode terminal; a second metal plate being joined with a bottom-surface electrode of a second switching element, and connected to a top-surface electrode of the first switching element; a third metal plate including a sixth mount part joined with a negative-electrode terminal, a seventh mount part connected to a top-surface electrode of the second switching element, and being narrower than the negative-electrode terminal, and a second narrow part between the sixth and seventh mount parts; and a snubber circuit connecting the first and second narrow parts.

A semiconductor device structure and method for manufacturing the same are provided. The semiconductor device structure includes a first metallization line, a second metallization line, a first isolation feature, a second isolation feature, a profile modifier, and a contact feature. The first metallization line and the second metallization line extend along a first direction. The first isolation feature and the second isolation feature are disposed between the first metallization line and the second metallization line. The first metallization line, the second metallization line, the first isolation feature and the second isolation feature define an aperture. The profile modifier is disposed within the aperture to modify a profile of the aperture in a plan view. The contact feature is disposed within the aperture.

This semiconductor device includes a first switching element, a second switching element, and a resin layer that seals each switching element. The semiconductor device includes: a power supply electrode which is formed on the surface of the resin layer and of which at least a part overlaps the first switching element when viewed from a z direction; and a power supply via conductor that electrically connects the first switching element and the power supply electrode through the resin layer in the z direction.

According to one embodiment, a semiconductor device includes a semiconductor member, an electrode portion, a pad portion, and first and second conductive members. The semiconductor member includes a first semiconductor layer and a second semiconductor layer. The electrode portion includes a source electrode, a gate electrode including a first gate portion, and a drain electrode. The first gate portion is between the source electrode and the drain electrode. The pad portion includes a drain pad. The first conductive member includes a first conductive portion. The drain pad is between the electrode portion and the first conductive portion. The second conductive member includes at least one of first to third conductive regions. The first conductive portion is between the drain pad and the first conductive region. The electrode portion is between the second conductive region and the third conductive region.

A semiconductor device is provided. For example, the semiconductor device can include a plurality of transistors that are arranged in an array in an X-Y plane. Each of the transistors can include a channel extending in Z direction. The semiconductor device can further include a plurality of word lines. Each of the word lines can electrically connect neighboring some of the transistors that are arranged in a column in X direction at lateral walls of the channels thereof. The semiconductor device can further include one or more electromagnetic shielding elements. At least one of the electromagnetic shielding elements can be disposed between neighboring two of the transistors that are disposed in a row in Y direction.

An integrated circuit device includes a radio frequency transistor amplifier die having a first surface, a second surface, a semiconductor layer structure that is between the first and second surfaces and includes a plurality of transistor cells adjacent the first surface, and terminals coupled to the transistor cells. At least one passive electronic component is provided on the second surface of the die and is electrically connected to at least one of the terminals, for example, by at least one conductive via. One or more conductive pillar structures may protrude from the first surface of the die to provide electrical connections to one or more of the terminals.

A semiconductor device of embodiments includes: a silicon carbide layer having a first face parallel to a first direction and a second direction crossing the first direction and a second face facing the first face; a first trench on a side of the first face extending in the first direction; a second trench extending in the first direction; a third trench extending in the second direction and continuous with the first trench and the second trench; a fourth trench extending in the first direction, disposed between the first trench and the second trench, and spaced from the third trench in the first direction; a gate electrode in the first to fourth trench; a gate insulating layer; a first conductive layer crossing the third trench and connected to the gate electrode; a first electrode disposed on the first face; and a second electrode disposed on the second face.

A high frequency semiconductor amplifier according to the present disclosure includes: a transistor formed on a semiconductor substrate and including a gate electrode, a source electrode, and a drain electrode; a matching circuit for input-side fundamental wave matching of the transistor; a first inductor formed on the semiconductor substrate and having one end connected to the gate electrode of the transistor and the other end connected to the matching circuit; a capacitor formed on the semiconductor substrate and having one end being short-circuited; and a second inductor formed on the semiconductor substrate and having one end connected to the gate electrode of the transistor and the other end connected to the other end of the capacitor, wherein the second inductor resonates in series with the capacitor at second harmonic frequency, has a mutual inductance of subtractive polarity with the first inductor, and the first inductor and the second inductor form mutual inductive circuits for input-side second harmonic matching.