All of four of built-in gate resistance trenches function as practical built-in gate resistance trenches. A first end portion of each of four of the built-in gate resistance trenches is electrically connected to a wiring side contact region of a gate wiring via a wiring contact. A second end portion of each of four of the built-in gate resistance trenches is electrically connected to a pad side contact region of a gate pad via a pad contact. In each of four of the built-in gate resistance trenches, a distance between the wiring contact and the pad contact is defined as an inter-contact distance.

An SiC semiconductor device includes an SiC semiconductor layer including an SiC monocrystal that is constituted of a hexagonal crystal and having a first main surface as a device surface facing a c-plane of the SiC monocrystal and has an off angle inclined with respect to the c-plane, a second main surface at a side opposite to the first main surface, and a side surface facing an a-plane of the SiC monocrystal and has an angle less than the off angle with respect to a normal to the first main surface when the normal is 0°.

A semiconductor device including an interconnect. The interconnect is arranged to transfer current from one terminal to another, and the interconnect includes a first layer including a plurality of interweaved fingers, and each of the interweaved fingers varies in width in a direction of propagation current thereby resulting in a difference of resistance within each of the interweaved fingers in the direction of propagation of current; a second layer arranged below the first layer. The second layer compensates for the difference of resistance in the first layer.

An integrated circuit structure includes a first metallization layer with first and second electrodes, each of which has electrode fingers. A second metallization layer may be included below the first metallization layer and include one or more electrodes with electrode fingers. The integrated circuit structure is configured to exhibit at least partial vertical inductance cancellation when the first electrode and second electrode are energized. The integrated circuit structure can be configured to also exhibit horizontal inductance cancellation between adjacent electrode fingers. Also disclosed is a simulation model that includes a capacitor model that models capacitance between electrode fingers having a finger length and includes at least one resistor-capacitor series circuit in which a resistance of the resistor increases with decreasing finger length for at least some values of the finger length.

A semiconductor structure including chips is provided. The chips are arranged in a stack. Each of the chips includes a radio frequency (RF) device. Two adjacent chips are bonded to each other. The RF devices in the chips are connected in parallel. Each of the RF devices includes a gate, a source region, and a drain region. The gates in the RF devices connected in parallel have the same shape and the same size. The source regions in the RF devices connected in parallel have the same shape and the same size. The drain regions in the RF devices connected in parallel have the same shape and the same size.

RF transistor amplifiers include an RF transistor amplifier die having a Group III nitride-based semiconductor layer structure and a plurality of gate terminals, a plurality of drain terminals, and at least one source terminal that are each on an upper surface of the semiconductor layer structure, an interconnect structure on an upper surface of the RF transistor amplifier die, and a coupling element between the RF transistor amplifier die and the interconnect structure that electrically connects the gate terminals, the drain terminals and the source terminal to the interconnect structure.

A method for manufacturing a semiconductor device includes forming semiconductor devices from a semiconductor wafer and identifying a position of the semiconductor device in the semiconductor wafer, wherein the forming the semiconductor devices includes forming a first repeating pattern including i semiconductor devices each having a unique pattern, forming a second repeating pattern including j semiconductor devices each having a unique pattern, defining semiconductor devices on the semiconductor wafer such that each of the k semiconductor devices has a unique pattern based on the first and second repeating patterns, and grinding a backside of the semiconductor wafer, wherein each unique pattern of the k semiconductor devices is composed of a combination of the unique patterns of the first and second repeating patterns, wherein the position of the semiconductor device is identified based on the unique patterns of the first and second repeating patterns and an angle of a grinding mark.

Example embodiments relate to a field-effect transistors having improved layouts. One example field-effect transistor includes a semiconductor substrate on which at least one transistor cell array is arranged. Each transistor cell includes a first transistor cell unit. Each first transistor cell unit includes a plurality of gate fingers, a main gate finger segment, a plurality of drain fingers, and a main drain finger segment. Each first transistor cell unit also includes a main gate finger base connected to the main gate finger segment of the first transistor cell unit and extending from that main gate finger segment towards the main drain finger segment of that first transistor cell unit. Further, each first transistor cell unit includes a main drain finger base connected to the main drain finger segment of that first transistor cell and extending from that main drain finger segment towards that main gate finger segment.

A substrate has an active area including first and second doped regions separated by portions of the substrate. Gates are located over the active area, each gate formed extending over a portion of the substrate separating adjacent first and second doped regions. A length of the doped regions is greater than other devices within the substrate that have a same gate oxide thickness. A first metallization layer has first electrical connectors between each of the first doped regions and a gate immediately adjacent thereto, and second electrical connectors connected to each of the second doped regions. A second metallization layer has a first electrical connector connected to each first electrical connector of the first metallization layer, and a second electrical connector connected to each second electrical connector of the first metallization layer, with the second electrical connector of the second metallization layer not overlapping the gates.

A high-frequency amplifier includes: a common-source transistor that has gate fingers, drain fingers, and source fingers, amplifies a signal applied to each of the gate fingers as a signal to be amplified, and outputs an amplified signal from each of the drain fingers; a common-gate transistor that has source fingers connected to the drain fingers of the common-source transistor, drain fingers, and gate fingers, and amplifies the amplified signal output from each of the drain fingers of the common-source transistor; a gate bus bar connected to the gate fingers of the common-gate transistor; and capacitors each having a first end connected to the gate bus bar and a second end grounded: wherein the capacitors are arranged at respective positions where impedances obtained by looking toward the respective capacitors from the respective gate fingers of the common-gate transistor are equal to each other.