An illustrative device disclosed herein includes a semiconductor substrate and a FinFET transistor device positioned above the semiconductor substrate, wherein the FinFET transistor device has a single active fin structure. The device also includes an electrically inactive dummy fin structure positioned adjacent the single active fin structure, wherein the electrically inactive dummy fin structure is electrically inactive with respect to electrical operation of the FinFET transistor having the single active fin.

According to an embodiment, provided is a semiconductor device includes a semiconductor layer; a first electrode; a second electrode; an electrode pad; a wiring layer electrically connected to the gate electrode; a first polycrystalline silicon layer electrically connected to the electrode pad and the wiring layer; and an insulating layer provided between the first polycrystalline silicon layer and the electrode pad and between the first polycrystalline silicon layer and the wiring layer and having a first opening and a second opening. The electrode pad and the first polycrystalline silicon layer are electrically connected via an inside of the first opening. The wiring layer and the first polycrystalline silicon layer are electrically connected via an inside of the second opening, A first opening area of the first opening is larger than a second opening area of the second opening.

Radio frequency (RF) power dies having flip-chip architectures are disclosed, as are power amplifier modules (PAMs) containing such RF power dies. Embodiment of the PAM include a module substrate and an RF power die, which is mounted to a surface of the module substrate in an inverted orientation. The RF power die includes, in turn, a die body having a frontside and an opposing backside, a transistor having active regions formed in the die body, and a frontside layer system formed over the die body frontside. The frontside layer system contains patterned metal layers defining first, second, and third branched electrode structures, which are electrically coupled to the active regions of the transistor. A frontside input/output interface is formed in an outer terminal portion of the frontside layer system and contains first, second, and third bond pads electrically coupled to the first, second, and third branched electrode structures, respectively.

The present disclosure relates to a semiconductor device with isolation and/or protection structures. A semiconductor device can include a substrate, a first transistor and a second transistor, wherein the first transistor and the second transistor are formed on the substrate, and an isolation structure formed on the substrate. The isolation structure can be formed on the substrate between the first transistor and the second transistor. The isolation structure can be configured to isolate the first transistor and the second transistor.

Radio frequency (RF) power dies having flip-chip architectures are disclosed, as are power amplifier modules (PAMs) containing such RF power dies. Embodiment of the PAM include a module substrate and an RF power die, which is mounted to a surface of the module substrate in an inverted orientation. The RF power die includes, in turn, a die body having a frontside and an opposing backside, a transistor having active regions formed in the die body, and a frontside layer system formed over the die body frontside. The frontside layer system contains patterned metal layers defining first, second, and third branched electrode structures, which are electrically coupled to the active regions of the transistor. A frontside input/output interface is formed in an outer terminal portion of the frontside layer system and contains first, second, and third bond pads electrically coupled to the first, second, and third branched electrode structures, respectively.

A diode, which is implemented in a semiconductor structure, includes a substrate, and first, second, third and fourth conductors. The substrate contains first and second doped regions. The first and second doped regions are used respectively as a first electrode and a second electrode of the diode. The first and third conductors are in a first conductor layer of the semiconductor structure and are connected to the first and second doped regions, respectively. The second and fourth conductors are in a second conductor layer of the semiconductor structure and are connected to the first and third conductors, respectively. In a side view of the semiconductor structure, an overlapping area between the first conductor and the third conductor is larger than an overlapping between of the second conductor and the fourth conductor.

A semiconductor device includes an active region formed in a substrate. The active region includes input fingers, output fingers, and common fingers disposed within the substrate and oriented substantially parallel to one another. An input port is electrically connected to the input fingers and an output port is electrically connected to the output fingers. A common region is electrically connected to the common fingers. At least one of the input and output ports is positioned within the active region between the input, output, and common fingers. The common region is interposed between a pair of the common fingers such that the common fingers of the pair are spaced apart by a gap, and at least one of the input and output ports is position in the gap.

A semiconductor memory device includes a first substrate; active or passive circuits on the first substrate; a second substrate above the active or passive circuits; gate electrodes stacked on the second substrate to be spaced apart from each other in a first direction; channel structures penetrating through the gate electrodes and extending in the first direction, and each including a channel layer; separation regions penetrating through the gate electrodes and extending in a second direction; a through-contact plug extending through the second substrate in the first direction and electrically connecting the gate electrodes and the active or passive circuits to each other; and a barrier structure spaced apart from the through-contact plug and surrounding the through-contact plug and having first regions each having a first width, and second regions each having a second width greater than the first width.

A transistor device includes a plurality of gate fingers that extend in a first direction and are spaced apart from each other in a second direction, each of the gate fingers comprising at least spaced-apart and generally collinear first and second gate finger segments that are electrically connected to each other. The first gate finger segments are separated from the second gate finger segments in the first direction by a gap region that extends in the second direction. A resistor is disposed in the gap region.

A high electron mobility transistor (HEMT) includes a channel layer comprising a group III-V compound semiconductor; a barrier layer comprising the group III-V compound semiconductor on the channel layer; a gate electrode on the barrier layer; a source electrode over gate electrode; a drain electrode spaced apart from the source electrode; and a metal wiring layer. A same layer of the metal wiring layer includes a gate wiring connected to the gate electrode, a source field plate connected to the source electrode, and a drain field plate connected to the drain electrode.