A lateral power semiconductor device with a metal interconnect layout for low on-resistance. The metal interconnect layout includes first, second, and third metal layers, each of which include source bars and drain bars. Source bars in the first, second, and third metal layers are electrically connected. Drain bars in the first, second, and third metal layers are electrically connected. In one embodiment, the first and second metal layers are parallel, and the third metal layer is perpendicular to the first and second metal layers. In another embodiment, the first and third metal layer are parallel, and the second metal layer is perpendicular to the first and third metal layers. A nonconductive layer ensures solder bumps electrically connect to only source bars or only drain bars. As a result, a plurality of available pathways exists and enables current to take any of the plurality of available pathways.

A multi-cell transistor includes a semiconductor structure, a plurality of unit cell transistors that are electrically connected in parallel, each unit cell transistor extending in a first direction in the semiconductor structure, wherein the unit cell transistors are spaced apart from each other along a second direction, and an isolation structure that is positioned between a first group of the unit cell transistors and a second group of the unit cell transistors and that extends above the semiconductor structure.

Implementations of a semiconductor package may include two or more die, each of the two more die coupled to a metal layer at a drain of each of the two more die, the two or more die and each metal layer arranged in two parallel planes; a first interconnect layer coupled at a source of each of the two more die; a second interconnect layer coupled to a gate of each of the two or more die and to a gate package contact through one or more vias; and an encapsulant that encapsulates the two or more die and at least a portion of the first interconnect layer, each metal layer, and the second interconnect layer.

The fabrication of field-effect transistor (FET) devices is described herein where the FET devices include one or more body contacts implemented between source, gate, drain (S/G/D) assemblies to improve the influence of a voltage applied at the body contact on the S/G/D assemblies. The FET devices can include source fingers and drain fingers interleaved with gate fingers. The source and drain fingers of a first S/G/D assembly can be electrically connected to the source and drain fingers of a second S/G/D assembly. The source fingers and the drain fingers can be arranged in alternating rows.

A method includes bonding a device die to an interposer. The interposer includes a through-via extending from a top surface of a semiconductor substrate of the interposer into an intermediate level between the top surface and a bottom surface of the semiconductor substrate. A singulation process is performed to saw the interposer and the device die into a package. The method further includes placing the package over a carrier, encapsulating the package in an encapsulant, thinning the encapsulant and the semiconductor substrate of the interposer until the through-via is exposed, and forming redistribution lines, wherein a redistribution line in the redistribution lines is in contact with the through-via.

The present disclosure describes a throughput-scalable sensing system. The system includes a plurality of semiconductor dies sharing a common semiconductor substrate and a plurality of transmembrane pore based sensors configured to detect a change of current flow as a result of analyzing biological or chemical samples. Two immediately neighboring transmembrane pore based sensors are arranged on respective two semiconductor dies separated by a dicing street. Each transmembrane pore based sensor is arranged on a separate semiconductor die of the plurality of semiconductor dies. At least one transmembrane pore based sensor includes one or more detection electrodes disposed above the common semiconductor substrate and a lipid bilayer disposed above the one or more detection electrodes.

The present disclosure describes a throughput-scalable photon sensing system. The system includes a plurality of semiconductor dies sharing a common semiconductor substrate and a plurality of photon detection sensors configured to perform a single molecule analysis of biological or chemical samples. Two immediately neighboring photon detection sensors are arranged on respective two semiconductor dies separated by a dicing street. Each photon detection sensor is arranged on a separate semiconductor die. The system further includes a first optical waveguide, a plurality of second optical waveguides disposed above the first optical waveguide, one or more wells disposed in the plurality of second optical waveguides, and one or more light guiding channels.

A method for fabricating a throughput-scalable sensing system is disclosed. The method includes receiving a first semiconductor wafer and a second semiconductor wafer. The first semiconductor wafer includes a semiconductor substrate and a plurality of sensors disposed in the semiconductor substrate. Each sensor of the plurality of sensors is disposed in a separate semiconductor die of the first semiconductor wafer. The method further includes bonding the first semiconductor wafer to the second semiconductor wafer and preparing the bonded first semiconductor wafer and the second semiconductor wafer for conductive path redistribution. The method further includes forming one or more redistribution paths and dicing an array of semiconductor dies as a group from the plurality of semiconductor dies. The array of semiconductor dies includes a group of sensors associated with the throughput-scalable sensing system.

Provided is a semiconductor device including: a semiconductor chip having a rectangular region including a first corner portion having a first notch portion, a second corner portion being provided to diagonally face the first corner portion, a third corner portion, and a fourth corner portion being provided to diagonally face the third corner portion on a surface and having a semiconductor element formed in the rectangular region; a first electrode including a fifth corner portion being provided on the first corner portion and having a second notch portion, a sixth corner portion being provided on the second corner portion, a seventh corner portion being provided on the third corner portion, and an eighth corner portion being provided on the fourth corner portion, the first electrode being provided on the semiconductor element, and the first electrode being electrically connected to the semiconductor element; and a first connector including a ninth corner portion being provided on the fifth corner portion and having a third notch portion and a twelfth corner portion being provided on the eighth corner portion, the first connector being provided on the first electrode, and the first connector being electrically connected to the first electrode.

A semiconductor device includes a substrate, a body structure and an electronic component. The body structure is disposed above the substrate and includes a semiconductor die, a molding compound, a conductive component and a lower redistribution layer (RDL). The semiconductor die has an active surface. The molding compound encapsulates the semiconductor die and has a lower surface, an upper surface opposite to the lower surface and a through hole extending to the upper surface from the lower surface. The conductive component is formed within the through hole. The lower RDL is formed on the lower surface of the molding compound, the active surface of the semiconductor die and the conductive component exposed from the lower surface. The electronic component is disposed above the upper surface of the molding compound and electrically connected to the lower RDL through the conductive component.