Because of inclusion of: a source electrode that is formed on a front surface of a semiconductor substrate and that is joined to the semiconductor substrate both at a source electrode as a first contact region that is an ohmic contact region and at a source electrode as a second contact region that is a contact region with a non-ohmic contact or the like; a back-surface electrode formed on a back surface of the semiconductor substrate; and a through hole in which an interconnection is provided that connects the source electrode as the second contact region in the source electrode with the back-surface electrode; it is possible not only to improve the corrosion resistance but also to reduce the leakage current, so that a highly-reliable semiconductor device suited for high frequency operation is provided.

A field effect transistor according to the present invention includes a semiconductor substrate, a plurality of drain electrodes provided on a first surface of the semiconductor substrate and extending in a first direction, an input terminal, an output terminal, and a plurality of metal layers provided in the semiconductor substrate apart from the first surface and extending in a second direction crossing the first direction, in which the plurality of metal layers include a first metal layer and a second metal layer which is longer than the first metal layer and which crosses more drain electrodes than the first metal layer when seen from a direction perpendicular to the first surface, and among the plurality of drain electrodes, those having a smaller length of line from the input terminal to the output terminal are provided with more metal layers directly thereunder.

Embodiments of this application disclose a package structure and a communications device to which the package structure is applied. The package structure includes a substrate, a die, and a bonding layer configured to bond the die to the substrate. Charged particles are disposed in the bonding layer. An electrode is disposed on a surface of the die away from the bonding layer. A potential of the electrode is opposite to that of the charged particle. The package structure further includes a first shielding structure. A potential of the substrate is zero. The first shielding structure is located on an outer surface of the die and is located between the bonding layer and the electrode, to prevent the charged particles from migrating to the electrode.

Gate fingers extending symmetrically from both sides of gate connecting portions, drain electrodes adjacent to both the gate fingers extending from both the sides of the gate connecting portions, and source electrodes respectively adjacent to the gate fingers extending from both the sides of the gate connecting portions are included. Gate air bridges connect the gate connecting portions and a gate routing line while straddling the source electrodes.

The present invention includes a method for creating a system in a package with integrated lumped element devices and active devices on a single chip/substrate for heterogeneous integration system-on-chip (HiSoC) in photo-definable glass, comprising: masking a design layout comprising one or more electrical passive and active components on or in a photosensitive glass substrate; activating the photosensitive glass substrate, heating and cooling to make the crystalline material to form a glass-crystalline substrate; etching the glass-crystalline substrate; and depositing, growing, or selectively etching a seed layer on a surface of the glass-crystalline substrate on the surface of the photodefinable glass.

According to one embodiment, a semiconductor device includes first to fourth electrodes, a semiconductor layer, a first extension conductive layer, first and second electrode connection portions, and an insulating member. The first to fourth electrodes extend along a first direction. The first electrode is between the second and third electrodes in a second direction. The second direction crosses the first direction. The first extension conductive layer extends along the first direction and is electrically connected to the first electrode. The fourth electrode is between the first and third electrodes in the second direction. The first electrode connection portion is electrically connected to the first electrode. The second electrode connection portion is electrically connected to the second and fourth electrodes. The insulating member includes a first insulating portion. The first insulating portion is between the second electrode connection portion and a portion of the first electrode.

An embodiment of a Doherty amplifier includes a module substrate, first and second surface-mount devices coupled to a top surface of the module substrate, and an impedance inverter line assembly. The first and second surface-mount devices include first and second amplifier dies, respectively. The impedance inverter line assembly is electrically connected between outputs of the first and second amplifier dies. The impedance inverter line assembly includes an impedance inverter line coupled to the module substrate, a first lead of the first surface-mount device coupled between the first amplifier die output and a proximal end of the impedance inverter line, and a second lead of the second surface-mount device coupled between the second amplifier die output and a distal end of the impedance inverter line. According to a further embodiment, the impedance inverter line assembly has a 90 degree electrical length at a fundamental operational frequency of the Doherty amplifier.

A semiconductor device according to the present embodiment comprises a first metallic line. The first metallic line is provided above a substrate and extends in a first direction with a first width. At least one second metallic line is connected to the first metallic line and extends in a second direction from the first metallic line with a second width that is smaller than the first width. A dummy metallic line is arranged adjacently to the at least one second metallic line, connected to the first metallic line, and extends in the second direction from the first metallic line. The dummy metallic line is not electrically connected to lines other than the first metallic line.

A line structure for fan-out circuit having a dense-line area and a fan-out area is provided. The line structure includes a plurality of dense lines arranged in the dense-line area parallel to a first direction, a plurality of pads disposed in the fan-out area, and a plurality of connecting lines arranged in the fan-out area parallel to a second direction. The connecting lines respectively connect one of the dense lines with one of the pads, wherein at least one of the connecting lines is a wavy line.

A packaged power device includes a ceramic package body having a top drain pad having a first area, a top source pad having a second area smaller than the first area, and a top gate pad having a third area smaller than the second area; a power device having a bottom surface affixed to a top drain pad, a die source pad coupled to the top source pad, and a die gate pad coupled to the top gate pad; and a ceramic lid affixed to the ceramic package body to form the packaged power device.