A semiconductor component is to be manufactured in a more time- and cost-efficient manner. The flexibility of the manufacturing process for the production of the semiconductor device is to be increased. This can be achieved with a semiconductor component (50), including a at least two functional units (2) which are identical to one another and are wired to one another, the identical functional units (2) each comprising at least one gate finger (16), at least one source finger (17) and at least one drain finger (18); the wiring comprising conductor tracks. A first track (26) connects the gate fingers (16) respectively, a second track (27) connects the source fingers (17) respectively, and a third track (28) connects the drain fingers (18) of the at least two same functional units (2) respectively. The method of manufacturing the semiconductor device (50) comprises (a) providing a first semiconductor wafer with a plurality of first functional units (2) which are identical to one another; (b) providing a second semiconductor wafer; (c) transferring at least two identical functional units (2) from the first semiconductor wafer to the second semiconductor wafer in one transfer step; and (d) wiring the two functional units (2) transferred to the second semiconductor wafer.

In a transistor formed on a semiconductor die mounted on a substrate, where the transistor output is connected to a circuit on the substrate, a bond pad electrically connected to a transistor drain finger manifold extends less than the full length of the manifold. By controlling the length of the bond pad, the parasitic capacitance it contributes may be controlled. In applications such as a Doherty amplifier, this parasitic capacitance forms part of the quarter-wave transmission line of an impedance inverter, and hence directly impacts amplifier performance. In particular, by reducing the parasitic capacitance contribution from transistor output bond pads, the bandwidth of a Doherty amplifier circuit may be improved. At GHz frequencies and with state of the art transistor device feature sizes, concerns about phase mismatch between drain finger outputs are largely moot.

A semiconductor device may include a semiconductor substrate, an upper electrode provided on an upper surface of the semiconductor substrate, a lower electrode provided on a lower surface of the semiconductor substrate, and a terminal connected to the upper electrode. The semiconductor substrate may include an active region in which switching elements are provided. The switching elements may be configured to pass a current between the upper electrode and the lower electrode. The active region may include a main region located under the terminal and an external region located outside the main region. The external region may include a low current region. A current density in the low current region may be lower than a current density in the main region in a case where the switching elements in the low current region and the main region are turned on.

A packaged power device includes a ceramic package body having a top drain pad having a first area, a top source pad having a second area smaller than the first area, and a top gate pad having a third area smaller than the second area; a power device having a bottom surface affixed to a top drain pad, a die source pad coupled to the top source pad, and a die gate pad coupled to the top gate pad; and a ceramic lid affixed to the ceramic package body to form the packaged power device.

A power transistor die includes a semiconductor die with input and output die sides, and a transistor integrally formed in the semiconductor die between the input die side and the output die side, where the transistor has an input and an output (e.g., a gate and a drain, respectively). The power transistor die also includes an input bondpad and a first output bondpad integrally formed in the semiconductor die between the input die side and the transistor. The input bondpad is electrically connected to the input of the transistor. A conductive structure directly electrically connects the output of the transistor to the first output bondpad. A second output bondpad, which also may be directly electrically connected to the transistor output, may be integrally formed in the semiconductor die between the transistor and the output die side.

Shielding techniques are used to provide an embedded sensor element such as a temperature sensing element on a wide bandgap power semiconductor device. A semiconductor device may include a drift layer and an embedded sensor element. The drift layer may be a wide bandgap semiconductor material. A shielding structure is provided in the drift layer below the embedded sensor element. The embedded sensor element may be provided between contacts that are in electrical contact with the shielding well. The distance between the contacts may be minimized. A noise reduction well may be provided between the contacts to further isolate the embedded sensor element from parasitic signals.

A power integrated module, including at least one first bridge formed in a chip, wherein the first bridge includes: a first upper bridge switch, formed by a plurality of first sub switches formed in the chip connected in parallel, and including a first, a second and a control end; a first lower bridge switch, formed by a plurality of second sub switches formed in the chip connected in parallel, and including a first, a second and a control end; a first electrode, connected to the first end of the first upper bridge switch; a second electrode, connected to the second end of the first lower bridge switch; and a third electrode, connected to the second end of the first upper bridge switch and the first end of the first lower bridge switch, wherein the first, the second and the third electrode are bar-type electrodes arranged side by side.

A semiconductor device is made by: forming a metal film containing Al on a surface of a substrate product including a substrate and a nitride semiconductor layer on the substrate, the metal film covering a via hole forming predetermined region, and the surface of the substrate product being located on the nitride semiconductor layer side, forming an etching mask having an opening for exposing the via hole forming predetermined region on a back surface of the substrate product, the back surface of the substrate product being located on the substrate side, and forming a via hole in the substrate product by reactive ion etching, the via hole reaching the surface from the back surface and exposing the metal film. In the forming of the via hole, a reaction gas containing fluorine is used during a period at least including a termination of etching.

The present disclosure describes a throughput-scalable photon sensing system. The system includes a plurality of semiconductor dies sharing a common semiconductor substrate and comprising one or more through-silicon vias. The system further includes a plurality of photon detection sensors configured to perform a single molecule or cluster sequencing analysis of biological or chemical samples. The system further includes a plurality of dicing streets separating the plurality of semiconductor dies from one another. Two immediately neighboring photon detection sensors of the plurality of photon detection sensors are arranged on respective two semiconductor dies separated by a dicing street of the plurality of dicing streets. A photon detection sensor comprises a plurality of sub-diffraction limit (SDL) photosensitive elements. Each SDL photosensitive element is sensitive to a single photoelectron. A single image pixel is generated based on one or more two-dimensional or three-dimensional arrays of outputs generated by SDL photosensitive elements.

A wire interconnect structure of an integrated circuit includes a first wiring layer, a second wiring layer, a third wiring layer, a first conductive via structure, a second conductive via structure, and a third conductive via structure. The first wiring layer includes a first wire connected to a first transistor and a second wire connected to a second transistor. The second wiring layer includes a third wire and a fourth wire that are perpendicular to the first wire and the second wire. The third wiring layer includes a fifth wire and a sixth wire that are parallel to the first wire and the second wire and respectively connected to a first contact pad and a second contact pad above. The first transistor is electrically connected to the first contact pad through the first wire, and the second transistor is electrically connected to the second contact pad through the second wire.