According to one embodiment, a semiconductor device includes: a semiconductor layer including a first plane extending along a plane including a first axis and a second axis; a first electrode extending along the first axis; a second electrode extending along the second axis; and a third electrode above the first plane. The third electrode is electrically coupled to the first electrode and the second electrode, and includes a first portion, a second portion and a third portion. The first portion crosses the first electrode. The second portion crosses the second electrode. The third portion crosses the second electrode and is separate at a first end from the second portion.

Some embodiments relate to a semiconductor device. The semiconductor device includes a layer disposed over a substrate. A conductive body extends through the layer. A plurality of bar or pillar structures are spaced apart from one another and laterally surround the conductive body. The plurality of bar or pillar structures are generally concentric around the conductive body.

A semiconductor die, which includes a first semiconductor device, a first passivation layer, and a first interconnect bump, is disclosed. The first passivation layer is over the first semiconductor device, which includes a first group of device fingers. The first interconnect bump is thermally and electrically connected to each of the first group of device fingers. Additionally, the first interconnect bump protrudes through a first opening in the first passivation layer.

A plurality of gate finger electrodes (2) is each arranged in a manner alternately adjacent to a corresponding one of drain electrodes (3) and a corresponding one of source electrode (4). The plurality of gate finger electrodes (2) is each connected to a corresponding one of gate routing lines (6). A resistor (7) has one end separating the gate routing lines (6) on respective two sides at a center portion between the gate routing lines (6), and has another end connected to an input line (10). Capacitors (8) are arranged on the respective two sides with respect to the resistor (7) and each connected to the corresponding gate routing line (6) by a corresponding one of air bridges (9).

An apparatus with a body layer disposed over a substrate is disclosed. The body layer has first and second diffusion areas with a first current collection area between the two. A plurality of first drain/source (D/S) diffusions spaced parallel with one another resides within the first diffusion area. A plurality of first channel regions resides within the first diffusion area such that each of the plurality of first channel regions resides between an adjacent pair of the plurality of the first D/S diffusions. A plurality of second D/S diffusions resides within the second diffusion area and are spaced parallel with one another. A plurality of second channel regions reside within the second diffusion area such that each of the plurality of second channel regions resides between an adjacent pair of the plurality of the second D/S diffusions. A first current collection diffusion resides within the first current collection area.

Embodiments of the present invention provide a multiple fin field effect transistor (finFET) with low-resistance gate structure. A metallization line is formed in parallel with the gate, and multiple contacts are formed over the fins which connect the metallization line to the gate. The metallization line provides reduced gate resistance, which allows fewer transistors to be used for providing In-Out (IO) functionality, thereby providing space savings that enable an increase in circuit density.

A method for forming a chip package structure is provided. The method includes forming a conductive via structure in a first substrate. The method includes bonding a chip to a first surface of the first substrate. The method includes forming a barrier layer over a second surface of the first substrate. The method includes forming a first insulating layer over the barrier layer. The method includes forming a conductive pad over the first insulating layer and in the first opening, the second opening, and the third opening. The conductive pad continuously extends from the conductive via structure into the third opening. The method includes forming a conductive bump over the conductive pad in the third opening.

A modular electronics package is disclosed that includes a first and second electronics packages, with each of the first and second electronics packages including a metallized insulating substrate and a solid-state switching device positioned on the metallized insulating substrate, the solid-state switching device comprising a plurality of contact pads electrically coupled to the first conductor layer of the metallized insulating substrate. A conductive joining material is positioned between the first electronics package and the second electronics package to electrically connect them together. The first electronics package and the second electronics package are stacked with one another to form a half-bridge unit cell, with the half-bridge unit cell having a current path through the solid-state switching device in the first electronics package and a close coupled return current path through the solid-state switching device in the second electronics package in opposite flow directions.

Pursuant to some embodiments of the present invention, transistor devices are provided that include a semiconductor structure, a gate finger extending on the semiconductor structure in a first direction, and a gate interconnect extending in the first direction and configured to be coupled to a gate signal at an interior position of the gate interconnect, where the gate interconnect is connected to the gate finger at a position offset from the interior position of the gate interconnect.

A high-frequency transistor includes a source electrode, a drain electrode, a gate electrode, and a gate drive line that applies a voltage to the gate electrode. An impedance adjustment circuit is connected between the gate electrode and the gate drive line. A characteristic impedance of the gate electrode is Z1, when a connecting point between the impedance adjustment circuit and the gate electrode is viewed from the impedance adjustment circuit. A characteristic impedance of the gate drive line is Z2, when a connecting point between the impedance adjustment circuit and the gate drive line is viewed from the impedance adjustment circuit. X that denotes a characteristic impedance of the impedance adjustment circuit is a value between Z1 and Z2.