A transistor includes an active region bounded by an outer periphery and formed in a substrate. The active region includes sets of input fingers, output fingers, and common fingers disposed within the substrate and oriented substantially parallel to one another. The transistor further includes an input port, an output port, a first via connection disposed at the outer periphery of the active region proximate the input port and a second via connection disposed at the outer periphery of the active region proximate the output port. The second via connection has a noncircular cross-section with a second major axis and a second minor axis, the second major axis having a second major axis length, the second minor axis having a second minor axis length that is less than the second major axis length. The second major axis is oriented parallel to a longitudinal dimension of the input, output, and common fingers.

Some embodiments relate to a semiconductor device. The semiconductor device includes a layer disposed over a substrate. A conductive body extends through the layer. A plurality of bar or pillar structures are spaced apart from one another and laterally surround the conductive body. The plurality of bar or pillar structures are generally concentric around the conductive body.

The present disclosure provides a semiconductor structure. The semiconductor structure includes a semiconductor substrate, a target layer, a plurality of metal pads, a plurality of conductive lines, a plurality of conductive plugs, an isolating liner, and a plurality of metal contacts. The semiconductor substrate has a front surface, a rear surface opposite to the front surface, and an implanted region connected to the rear surface. The target layer is disposed over the front surface. The metal pads are disposed over the target layer. The plurality of conductive lines are disposed within the semiconductor substrate and the target layer and connected to the metal pads. The conductive plugs are disposed in the implanted region. The isolating liner encircles the conductive plugs. The metal contacts are disposed over the conductive lines and the conductive plugs.

A semiconductor chip having a pad, a protective element, and an internal circuit for providing a semiconductor chip having a protective circuit with high noise resistance, wherein the semiconductor chip is characterized in that the resistance value of metal wiring on a path reaching the pad and the protective element is higher than the resistance value of the protective element.

A semiconductor device includes a plurality of unit cell transistors on a common semiconductor structure, the unit cell transistors electrically connected in parallel, and each unit cell transistor including a respective gate finger. Respective threshold voltages of first and second of the unit cell transistors differ by at least 0.1 volts and/or threshold voltages of first and second segments of a third of the unit cell transistors differ by at least 0.1 volts.

Disclosed is a semiconductor package. The semiconductor package may include a substrate a semiconductor chip mounted over a surface of the substrate such that an active surface of the semiconductor chip faces the surface of the substrate. The semiconductor chip and substrate may be configured for shielding or scattering electromagnetic waves.

A feed structure for an electrical component includes a slot structure with first and second longitudinal sections opposing one another and first and second interconnect segments opposing one another. The first and second interconnect segments couple the first longitudinal section with the second longitudinal section to form an opening extending through the slot structure, the opening being surrounded by the first longitudinal section, the first interconnect segment, the second longitudinal section, and the second interconnect segment. A first feed node is electrically connected to the slot structure at an intermediate region between first and second ends of the first longitudinal section, and second feed nodes are electrically coupled to the slot structure along the second longitudinal section. In a device or module, the second feed nodes are configured for electrical connection to the electrical component.

A multi-cell transistor includes a semiconductor structure, a plurality of unit cell transistors that are electrically connected in parallel, each unit cell transistor extending in a first direction in the semiconductor structure, wherein the unit cell transistors are spaced apart from each other along a second direction, and an isolation structure that is positioned between a first group of the unit cell transistors and a second group of the unit cell transistors and that extends above the semiconductor structure.

According to an aspect of the present disclosure, a semiconductor device is provided that includes a substrate, at least one bond pad, a passivation layer and a NBLoK layer. The bond pad is formed over the substrate. The passivation layer is deposited over the substrate and has an opening defined by end portions of the passivation layer over the bond pad. The NBLoK layer is covering the end portions of the passivation layer.

A transistor includes a semiconductor substrate having an active device region formed therein and an interconnect structure on a first surface of the semiconductor substrate. The interconnect structure is formed of multiple layers of dielectric material and electrically conductive material. Drain and gate runners are formed in the interconnect structure. A shield structure extends above a second surface of the interconnect structure, the shield structure being positioned between the drain and gate runners.