A semiconductor die, which includes a first semiconductor device, a first passivation layer, and a first interconnect bump, is disclosed. The first passivation layer is over the first semiconductor device, which includes a first group of device fingers. The first interconnect bump is thermally and electrically connected to each of the first group of device fingers. Additionally, the first interconnect bump protrudes through a first opening in the first passivation layer.

A short-channel metal oxide semiconductor varactor may include a source region of a first polarity having a source via contact. The varactor may further include a drain region of the first polarity having a drain via contact. The varactor may further include a channel region of the first polarity between the source region and the drain region. The channel region may include a gate. The varactor may further include at least one self-aligned contact (SAC) on the gate and between the source via contact and the drain via contact.

An integrated semiconductor device includes an Si substrate, and a high-side transistor and a low-side transistor which configure a half-bridge. A source electrode of a unit transistor configuring the high-side transistor and a drain electrode of a unit transistor configuring the low-side transistor are integrated as a common electrode.

A system and method for forming a semiconductor die contact structure is disclosed. An embodiment comprises a top level metal contact, such as copper, with a thickness large enough to act as a buffer for underlying low-k, extremely low-k, or ultra low-k dielectric layers. A contact pad or post-passivation interconnect may be formed over the top level metal contact, and a copper pillar or solder bump may be formed to be in electrical connection with the top level metal contact.

Gate fingers extending symmetrically from both sides of gate connecting portions, drain electrodes adjacent to both the gate fingers extending from both the sides of the gate connecting portions, and source electrodes respectively adjacent to the gate fingers extending from both the sides of the gate connecting portions are included. Gate air bridges connect the gate connecting portions and a gate routing line while straddling the source electrodes.

A semiconductor device includes an active layer having first and second active regions, first and second source electrodes, first and second drain electrodes, first and second gate electrodes, a first source metal layer, first and second drain metal layers, and a source pad electrically connected to the first source metal layer. The second drain metal layer is electrically connected to the second drain electrode and the first source metal layer. A projection of the second drain metal layer on the active layer forms a drain metal layer region. An projection of the source pad on the active layer forms a source pad region. An area of an overlapping region between the source pad region and the drain metal layer region is smaller than or equal to 40% of an area of the drain metal layer region.

A semiconductor device is provided with: a source wiring electrically coupled to the source electrode of a transistor; a drain wiring electrically coupled to the drain electrode of the transistor; a source pad electrically coupled to the source wiring; and, a drain pad electrically coupled to the drain wiring. The source wiring includes a first source wiring section and a second source wiring section having a width greater than that of the first source wiring section. The drain wiring includes a first drain wiring section and a second drain wiring section having a width greater than that of the first drain wiring section. The source pad at least partially overlaps the second drain wiring section in plan view. The drain pad at least partially overlaps the second source wiring section in plan view.

A transistor device includes a gate finger and a drain finger extending on a semiconductor structure, a gate bond pad coupled to the gate finger, and a drain bond pad coupled to the drain finger. The gate bond pad extends on the gate finger and the drain finger.

A transistor semiconductor die includes a drift layer, a first dielectric layer, a first metallization layer, a second dielectric layer, a second metallization layer, a first plurality of electrodes, and a second plurality of electrodes. The first dielectric layer is over the drift layer. The first metallization layer is over the first dielectric layer such that at least a portion of the first metallization layer provides a first contact pad. The second dielectric layer is over the first metallization layer. The second metallization layer is over the second dielectric layer such that at least a portion of the second metallization layer provides a second contact pad and the second metallization layer at least partially overlaps the first metallization layer. The transistor semiconductor die is configured to selectively conduct current between the first contact pad and a third contact pad based on signals provided at the second contact pad.

Some embodiments relate to a semiconductor device. The semiconductor device includes a layer disposed over a substrate. A conductive body extends through the layer. A plurality of bar or pillar structures are spaced apart from one another and laterally surround the conductive body. The plurality of bar or pillar structures are generally concentric around the conductive body.