Disclosed is a semiconductor package. The semiconductor package may include a substrate a semiconductor chip mounted over a surface of the substrate such that an active surface of the semiconductor chip faces the surface of the substrate. The semiconductor chip and substrate may be configured for shielding or scattering electromagnetic waves.

The present disclosure relates a method of forming an integrated chip packaging device. In some embodiments, the method may be performed by forming a conductive trace on a surface of a packaging component. The conductive trace has an angled surface defining an undercut. A molding material is deposited over an entirety of the conductive trace and within the undercut. The molding material is removed from an upper surface of the conductive trace. The molding material has a sloped outermost sidewall after removing the molding material from the upper surface. A solder region is formed on the upper surface of the conductive trace.

Implementations of semiconductor devices may include: a first layer with a plurality of cells, each cell having a drain finger, a source finger and a gate ring; a second layer having a drain pad and a source pad, the drain pad having a width and a source pad having a width substantially the same as the drain pad; wherein a width of each drain finger of the first layer is wider than a width of each source finger of the first layer; and wherein each drain pad is coupled to each drain finger through a first contact and the source pad is coupled to each source finger through a second contact, where a width of the first contact is wider than a width of the second contact.

There is provided a field-effect transistor including: a gate electrode; a semiconductor layer having a source region and a drain region with the gate electrode in between; contact plugs provided on the source region and the drain region; first metals stacked on the contact plugs; and a low-dielectric constant region provided in a region between the first metals along an in-plane direction of the semiconductor layer and provided at least in a first region below bottom surfaces of the first metals along a stacking direction.

A first interconnect on an interconnect level connects a first subset of PMOS drains together of a CMOS device. A second interconnect on the interconnect level connects a second subset of the PMOS drains together. The second subset of the PMOS drains is different than the first subset of the PMOS drains. The first interconnect and the second interconnect are disconnected on the interconnect level. A third interconnect on the interconnect level connects a first subset of NMOS drains together of the CMOS device. A fourth interconnect on the interconnect level connects a second subset of the NMOS drains together. The second subset of the NMOS drains is different than the first subset of the NMOS drains. The third interconnect and the fourth interconnect are disconnected on the interconnect level. The first, second, third, and fourth interconnects are coupled together through at least one other interconnect level.

Stripe-shaped surface transistor structures of a power MOSFET are disposed over an array of parallel-extending P type Buried Stripe-Shaped Charge Compensation Regions (BSSCCRs). The power MOSFET has two and only two epitaxial semiconductor layers, and the BSSCCRs are disposed at the interface between these layers. Looping around the area occupied by these parallel-extending BSSCCRs is a P type ring-shaped BSSCCR. At the upper semiconductor surface are disposed three P type surface rings. The inner surface ring and outer surface ring are coupled together by a bridging metal member, but the center surface ring is floating. The bridging metal member is disposed at least in part over the ring-shaped BSSCCR. The MOSFET has a high breakdown voltage, a low R.sub.DS(ON), and is acceptable and suitable for manufacture at semiconductor fabrication. plants that cannot or typically do not make superjunction MOSFETs.

High power transistors, such as high power gallium nitride (GaN) transistors, are described. These high power transistors have larger total gate widths than conventional high power transistors by arranging multiple linear arrays of gate, drain, and source contacts in parallel. Thereby, the total gate width and the power rating of the high power transistor may be increased without elongating the die of the high power transistor. Accordingly, the die of the high power transistor may be mounted in a smaller circuit package relative to conventional dies with the same power rating.

A semiconductor device includes a channel layer formed over a substrate, a barrier layer formed on the channel layer and a gate electrode. A second gate electrode section is formed on the gate electrode via a gate insulating film. It becomes possible to make an apparent threshold voltage applied to the second gate electrode of a MISFET higher than an original threshold voltage applied to the gate electrode for forming a channel under the gate electrode by providing an MIM section configured by the gate electrode, the gate insulating film and the second gate electrode in this way.

A print head substrate includes: a substrate surface including a plurality of printing elements and a plurality of pads disposed along a first side and electrically connected to the printing elements, the substrate surface having an acute angle portion formed by the first side and a second side; and a test element group (TEG) area including a TEG not electrically connected to the printing elements, at least a part of the TEG area being located between the second side and a pad closest to a vertex of the acute angle portion among the pads.

A transistor includes a plurality of gate fingers that extend in a first direction and are spaced apart from each other in a second direction, each of the gate fingers comprising at least spaced-apart and generally collinear first and second gate finger segments that are electrically connected to each other. The first gate finger segments are separated from the second gate finger segments in the first direction by a gap region that extends in the second direction. A resistor is disposed in the gap region.