A semiconductor device includes a gate electrode, first and second transistors arranged in a first direction, first and second drain wirings each connected to a corresponding drain region of the first and second transistors, first output wiring extending in a second direction orthogonal to the first direction and having one end connected to a portion adjacent to the second transistor of the first drain wiring, second output wiring extending in the second direction and having one end connected to a portion adjacent to the first transistor of the second drain wiring, third output wiring extending in the first direction and connected to the other end of the first output wiring and the other end of the second output wiring, and fourth output wiring connecting a center portion of the third output wiring to an output terminal.

A portion of a source pad is exposed in an opening of a passivation film. In the exposed portion of the source pad, a wiring region in which a package wiring member is to be bonded and a probe region that is a region different from the wiring region are provided. The probe region has a probe mark of a probe for an energization inspection. An area of the probe mark that overlaps the wiring region is at most 30% of an entire area of the wiring region in a plan view of the silicon carbide semiconductor device.

Provided is a semiconductor device which includes: a 1.sup.st source/drain region; a 2.sup.nd source/drain region with a 2.sup.nd contact plug thereon; a 3.sup.rd source/drain region; a 2.sup.nd metal line on the 2.sup.nd contact plug with a 2.sup.nd via therebetween; a 1.sup.st additional metal line on the 2.sup.nd contact plug with a 1.sup.st additional via therebetween, wherein the 2.sup.nd source/drain region is disposed between and connected to the 1.sup.st source/drain region and the 3.sup.rd source/drain region, and wherein the 2.sup.nd metal line and the 1.sup.st additional metal line are spaced apart from each other on the 2.sup.nd contact plug by a 1.sup.st predetermined distance in a 2.sup.nd horizontal direction.

A side-exposed embedded trace substrate includes a dielectric layer, a first wiring layer and a first wiring layer embedded in the dielectric layer. An outer surface of the first wiring layer is not higher than a surface of the dielectric layer, and the first wiring layer includes a pad having a groove to increase a side-exposed area of the pad. The contact area between the substrate and the solder during package welding is increased so that the welding reliability is enhanced, the problem of poor welding or poor reliability caused by trace embedding may be avoided, and poor filling of the packaging material due to insufficient gap between the device and the pad during packaging may be prevented.

The semiconductor device includes a semiconductor layer which has a main surface, a switching device which is formed in the semiconductor layer, a first electrode which is arranged on the main surface and electrically connected to the switching device, a second electrode which is arranged on the main surface at an interval from the first electrode and electrically connected to the switching device, a first terminal electrode which has a portion that overlaps the first electrode in plan view and a portion that overlaps the second electrode and is electrically connected to the first electrode, and a second terminal electrode which has a portion that overlaps the second electrode in plan view and is electrically connected to the second electrode.

All of four of built-in gate resistance trenches function as practical built-in gate resistance trenches. A first end portion of each of four of the built-in gate resistance trenches is electrically connected to a wiring side contact region of a gate wiring via a wiring contact. A second end portion of each of four of the built-in gate resistance trenches is electrically connected to a pad side contact region of a gate pad via a pad contact. In each of four of the built-in gate resistance trenches, a distance between the wiring contact and the pad contact is defined as an inter-contact distance.

There is provided a semiconductor device including a multi-gate transistor having a plurality of gates in a common active region, in which the multi-gate transistor has a comb-shaped metal structure in which a first metal is drawn out and bundled in a W length direction from contacts arranged in a single row in each of a source region and a drain region, and the multi-gate transistor has a wiring layout in which a root section of the first metal coincides immediately above an end of the source region and the drain region or is disposed inside the end of the source region and the drain region in the W length direction.

The semiconductor device includes a semiconductor layer which has a main surface, a switching device which is formed in the semiconductor layer, a first electrode which is arranged on the main surface and electrically connected to the switching device, a second electrode which is arranged on the main surface at an interval from the first electrode and electrically connected to the switching device, a first terminal electrode which has a portion that overlaps the first electrode in plan view and a portion that overlaps the second electrode and is electrically connected to the first electrode, and a second terminal electrode which has a portion that overlaps the second electrode in plan view and is electrically connected to the second electrode.

A semiconductor device includes a semiconductor substrate, a gate insulator provided on a surface of the semiconductor substrate, a bonding film, including silicon or aluminum, provided on the gate insulator, and a gate pad layer provided above the bonding film, wherein the gate pad layer includes titanium in at least a region in contact with the bonding film.

Stripe-shaped surface transistor structures of a power MOSFET are disposed over an array of parallel-extending P type Buried Stripe-Shaped Charge Compensation Regions (BSSCCRs). The power MOSFET has two and only two epitaxial semiconductor layers, and the BSSCCRs are disposed at the interface between these layers. Looping around the area occupied by these parallel-extending BSSCCRs is a P type ring-shaped BSSCCR. At the upper semiconductor surface are disposed three P type surface rings. The inner surface ring and outer surface ring are coupled together by a bridging metal member, but the center surface ring is floating. The bridging metal member is disposed at least in part over the ring-shaped BSSCCR. The MOSFET has a high breakdown voltage, a low R.sub.DS(ON), and is acceptable and suitable for manufacture at semiconductor fabrication plants that cannot or typically do not make superjunction MOSFETs.