High power transistors, such as high power gallium nitride (GaN) transistors, are described. These high power transistors have larger total gate widths than conventional high power transistors by arranging multiple linear arrays of gate, drain, and source contacts in parallel. Thereby, the total gate width and the power rating of the high power transistor may be increased without elongating the die of the high power transistor. Accordingly, the die of the high power transistor may be mounted in a smaller circuit package relative to conventional dies with the same power rating.

Embodiments of radio frequency (RF) devices are disclosed having interconnection paths with capacitive structures having improved quality (Q) factors. In one embodiment, an RF device includes an inductor having an inductor terminal and a semiconductor die. The semiconductor die includes one or more active semiconductor devices that include a device contact. The device contact provided by the one or more active semiconductor devices is positioned so as to be vertically aligned directly below the inductor terminal. The inductor terminal and the device contact are electrically connected with an interconnection path that includes a capacitive structure. To prevent or reduce current crowding, the interconnection path is vertically aligned so as to extend directly between the inductor terminal and the device contact. In this manner, the interconnection path electrically connects the inductor terminal and the device contact without degrading the Q factor of the RF device.

The present invention discloses an implementation method for stacked connection between isolated circuit components, whose setting is according to at least two circuit components connecting in parallel/series in a circuit, wherein, in accordance with a circuit connection configuration, a plurality of corresponding pins of the components are soldered directly, making the components form an integrated module in accordance with a desired connection configuration of the circuit, and saving circuit boards and wires. Comparing to the circuit limited in a PCB in the prior art, it is possible to construct a circuit unit by welding connection in a way of building-block approach, achieving a circuit in a 3D space through directly welding between components, and owning a wider design space, it may shorten the time used for a circuit from design to process.

A semiconductor device includes a semiconductor layer having an element formation region in which a semiconductor element is formed. An element isolation well is formed in a surface portion of the semiconductor layer to isolate the element formation region. A field insulating film is formed on a surface of the semiconductor layer. The field insulating film surrounds the element formation region in an annular shape when viewed from a top. An interlayer insulating film is formed on the semiconductor layer. A wiring is formed on the interlayer insulating film. A conductive film is formed on the field insulating film.

Embodiments include packaged semiconductor devices and methods of manufacturing packaged semiconductor devices. A semiconductor die includes a conductive feature coupled to a bottom surface of the die. The conductive feature only partially covers the bottom die surface to define a conductor-less region that spans a portion of the bottom die surface. The die is encapsulated by attaching the encapsulant material to the bottom die surface (e.g., including over the conductor-less region). The encapsulant material includes an opening that exposes the conductive feature. After encapsulating the die, a heatsink is positioned within the opening, and a surface of the heatsink is attached to the conductive feature. Because the heatsink is attached after encapsulating the die, the heatsink sidewalls are not directly bonded to the encapsulant material.

Implementations of semiconductor devices may include: a first layer with a plurality of cells, each cell having a drain finger, a source finger and a gate ring; a second layer having a drain pad and a source pad, the drain pad having a width and a source pad having a width substantially the same as the drain pad; wherein a width of each drain finger of the first layer is wider than a width of each source finger of the first layer; and wherein each drain pad is coupled to each drain finger through a first contact and the source pad is coupled to each source finger through a second contact, where a width of the first contact is wider than a width of the second contact.

A semiconductor device of the present invention includes a semiconductor layer including a main IGBT cell and a sense IGBT cell connected in parallel to each other, a first resistance portion having a first resistance value formed using a gate wiring portion of the sense IGBT cell and a second resistance portion having a second resistance value higher than the first resistance value, a gate wiring electrically connected through mutually different channels to the first resistance portion and the second resistance portion, a first diode provided between the gate wiring and the first resistance portion, a second diode provided between the gate wiring and the second resistance portion in a manner oriented reversely to the first diode, an emitter electrode disposed on the semiconductor layer, electrically connected to an emitter of the main IGBT cell, and a sense emitter electrode disposed on the semiconductor layer, electrically connected to an emitter of the sense IGBT cell.

A power transistor includes a plurality of transistor cells. Each transistor cell has a first electrode coupled to a first electrode interconnection region overlying a first major surface, a control electrode coupled to a control electrode interconnection region overlying the first major surface, and a second electrode coupled to a second electrode interconnection region overlying a second major surface. Each transistor cell has an approximately constant doping concentration in the channel region. A dielectric platform is used as an edge termination of an epitaxial layer to maintain substantially planar equipotential lines therein. The power transistor finds particular utility in radio frequency applications operating at a frequency greater than 500 megahertz and dissipating more than 5 watts of power. The semiconductor die and package are designed so that the power transistor can efficiently operate under such severe conditions.

RF communications circuitry, which includes a first RF filter structure, is disclosed. The first RF filter structure includes a first tunable RF filter path and a second tunable RF filter path. The first tunable RF filter path includes a pair of weakly coupled resonators. Additionally, a first filter parameter of the first tunable RF filter path is tuned based on a first filter control signal. A first filter parameter of the second tunable RF filter path is tuned based on a second filter control signal.

A Doherty amplifier comprises a main amplifier and a peaking amplifier. The main amplifier and the peaking amplifier are electrically connected to a same input signal source. The main amplifier and the peaking amplifier comprise different epitaxial structures of a Group III nitride material. To form the Doherty amplifier, the main amplifier and the peaking amplifier are formed comprising Group III nitride transistors comprising different epitaxial structures from different epiwafers such that the Group III nitride transistors of the main and peaking amplifiers comprise different epitaxial structures. The wafers are diced to produce respective amplifier dies comprising the main amplifier and peaking amplifier, respectively. The amplifier dies are mounted on a common heat sink, and the main and peaking amplifiers are electrically connected to the input signal source.