A semiconductor device package may include a leadframe having a first portion with first extended portions and a second portion with second extended portions. Mold material may encapsulate a portion of the leadframe and a portion of a semiconductor die mounted to the leadframe. A first set of contacts of the semiconductor die may be connected to a first surface of the first extended portions, while a second set of contacts may be connected to a first surface of the second extended portions. A mold-locking cavity having the mold material included therein may be disposed in contact with a second surface of the first extended portions opposed to the first surface of the first extended portions, a second surface of the second extended portions opposed to the first surface of the second extended portions, the first portion of the leadframe, and the second portion of the leadframe.

To provide a technique of reducing gate oscillation while suppressing reduction in switching speed. A semiconductor device according to the technique disclosed in the present description includes: a first gate electrode in an active region; a gate pad in a first region different from the active region in a plan view; and a first gate line electrically connecting the first gate electrode and the gate pad to each other. The first gate line is formed into a spiral shape. The first gate line is made of a different type of material from the first gate electrode.

A semiconductor device includes a substrate, a first unit FET including first source, first drain, and first gate electrodes, a second unit FET including second source, second drain, and second gate electrodes, a first source wiring electrically contacting the first source electrode, a gate bus bar electrically connected to the first gate electrode, and interposing the first gate electrode between the gate bus bar and the second gate electrode, and a gate wiring provided above the first source electrode in non-contact with the first source electrode, and electrically connecting the gate bus bar and the second gate electrode, wherein a maximum width in a first direction of a region where the first source wiring contacts the first source electrode is times or more a maximum width in the first direction of a region where the first source wiring overlaps the first source electrode.

The disclosure a three-dimensional integrated system with a compatible chip and a manufacturing method thereof, which extends at least one functional chip to form an expanded chip including a functional chip and a peripheral pad. And a pad of the functional chip is electrically drawn out to the peripheral pads by rewiring. Based on an alignment bonding of the two expanded chips corresponding to the peripheral pads, or based on an alignment bonding of the functional chip and the expanded chip, an electrical connection and three-dimensional integration between two functional chips is completed simply and effectively. An integrated connection between two independent functional chips is realized based on the peripheral expanded pads. Each functional chip may be manufactured with its own independent process system.

A semiconductor device includes a nitride-based transistor, a first metal layer, a second metal layer, a third metal layer, a source pad, and a drain pad. The first metal layer is disposed over the nitride-based transistor. The second metal layer is disposed over the first metal layer. The third metal layer is disposed over the second metal layer and includes a first pattern and a second pattern which are spaced apart from each other. The source pad is immediately above the first metal layer, the second metal layer, and the first pattern of the third metal layer and is electrically coupled with the nitride-based transistor. The drain pad is immediately above the first metal layer, the second metal layer, and the second pattern of the third metal layer and is electrically coupled with the nitride-based transistor.

Three-dimensional (3-D) integrated circuit structures and circuits that enable high performance FET switch arrays while consuming less planar area than conventional 2-D IC dies. In one embodiment, an integrated FET switch circuit includes a first wafer/die including a first set of groups of FET cells, and a second wafer/die joined to the first wafer/die through hybrid bonding interconnects and including a second set of groups of FET cells, wherein a first side drain bus of each group in the first wafer/die is connected through the hybrid bonding interconnects to a second side source bus of a first corresponding group in the second wafer/die; and wherein a second side source bus of each group in the first wafer/die is connected through the hybrid bonding interconnects to a first side drain bus of a second corresponding group in the second wafer/die.

A semiconductor device includes a semiconductor element, a first lead, a second lead and a connection lead. The semiconductor element includes an electron transit layer formed of a nitride semiconductor, an element obverse face and an element reverse face that are arranged to face opposite to each other in a thickness direction, and a gate electrode, a source electrode and a drain electrode that are disposed on the element obverse face. The drain electrode is bonded to the first lead. The source electrode is bonded to the second lead. The connection lead is connected to the second lead and disposed on the element reverse face so as to overlap with the semiconductor element as viewed in the thickness direction. The connection lead provides a conduction path for a principal current subjected to switching.

A transistor amplifier includes a semiconductor layer structure comprising first and second major surfaces and a plurality of unit cell transistors on the first major surface that are electrically connected in parallel, each unit cell transistor comprising a gate finger coupled to a gate manifold, a drain finger coupled to a drain manifold, and a source finger. The semiconductor layer structure is free of a via to the source fingers on the second major surface.

A heterojunction power device includes: a substrate containing semiconductor material; a first active area and a second active area, arranged on the substrate symmetrically opposite with respect to an axis of symmetry and accommodating respective heterostructures; a separation region, extending along the axis of symmetry between the first active area and the second active area. The power device further includes: a first conductive bus configured to distribute a first electric potential of the power device in parallel to the first and the second active areas; a second conductive bus configured to distribute a second electric potential of the power device, different from the first electric potential, in parallel to the first and the second active areas. The first and the second conductive buses extend along the axis of symmetry above the separation region and the second conductive bus overlies the first conductive bus.

Representative techniques and devices including process steps may be employed to mitigate the potential for delamination of bonded microelectronic substrates due to metal expansion at a bonding interface. For example, a through-silicon via (TSV) may be disposed through at least one of the microelectronic substrates. The TSV is exposed at the bonding interface of the substrate and functions as a contact surface for direct bonding.