A semiconductor memory device includes a first chip having a peripheral transistor and a first insulating layer, and includes a second chip having a stacked structure and a second insulating layer. The stacked structure includes conductive patterns and insulating patterns alternately stacked with each other, the first insulating layer includes a first bonding surface, the second insulating layer includes a second bonding surface contacting the first bonding surface, and the second chip further includes a protrusion protruding from the second bonding surface of the second insulating layer toward the first insulating layer.

The present application discloses a semiconductor device and a method for fabricating the semiconductor device. The semiconductor device includes a substrate, a pad structure positioned above the substrate, and a top groove positioned on a top surface of the pad structure. The method for fabricating the semiconductor device includes forming a pad structure over a substrate and forming a top groove on a top surface of the pad structure.

A electronic component includes a connection electrode on a wiring layer. An electrically conductive layer is connected to the wiring layer via the connection electrode. A protective film covers a cover portion and the electrically conductive layer. A solder bump is electrically connected to the electrically conductive layer via an opening. An alloy layer is between the solder bump and the electrically conductive layer in a thickness direction to join the solder bump to the electrically conductive layer and differs in composition and/or elements from the solder bump. The connection electrode does not overlap the solder bump. The surface of the electrically conductive layer that is located on a protective film side is in contact with the protective film between the alloy layer and an edge of the electrically conductive layer that is located on a connection electrode side.

A semiconductor device includes a semiconductor element having first and second main surfaces spaced apart in a thickness direction. The semiconductor element includes a metal underlying layer on the first main surface, a bonding pad on the metal underlying layer with a wire bonded to the pad, and an insulative protection layer formed on the first main surface and surrounding the bonding pad. The bonding pad includes first and second conductive layers. The first conductive layer covers the metal underlying layer and is made of a metal having a lower ionization tendency than the metal underlying layer. The second conductive layer covers the first conductive layer and is made of a metal having a lower ionization tendency than the first conductive layer. The first and second conductive layers have respective peripheries held in close contact with the protection layer and covering a part of the protection layer.

Disclosed herein is a package comprising a first redistribution layer (RDL) disposed on a first side of a first semiconductor substrate and a second RDL disposed on a second semiconductor substrate, wherein the first RDL is bonded to the second RDL. First conductive elements are disposed in the first RDL and the second RDL. First vias extend from one or more of the first conductive elements through the first semiconductor substrate to a second side of the first semiconductor substrate opposite the first side. First spacers are interposed between the first semiconductor substrate and the first vias and each extend from a respective one of the first conductive elements through the first semiconductor substrate.

A semiconductor device assembly includes a semiconductor die, a substrate, and a spacer directly coupled to the substrate. The spacer includes a flexible main body and a support structure embedded in the flexible main body, wherein the support structure has a higher stiffness than the flexible main body. The spacer carries the semiconductor die. The flexible main body of the spacer mitigates the effects of thermomechanical stress, for example caused by a mismatch between the coefficient of thermal expansion of the semiconductor die and the substrate. The embedded support structure provides strength needed to support the semiconductor die during assembly.

A device for controlling trapped ions includes a first semiconductor substrate. A second semiconductor substrate is disposed over the first semiconductor substrate. At least one ion trap is configured to trap ions in a space between the first semiconductor substrate and the second semiconductor substrate. A spacer is disposed between the first semiconductor substrate and the second semiconductor substrate, the spacer including an electrical interconnect which electrically connects a first metal layer structure of the first semiconductor substrate to a second metal layer structure of the second semiconductor substrate.

A semiconductor device includes a semiconductor element having first and second main surfaces spaced apart in a thickness direction. The semiconductor element includes a metal underlying layer on the first main surface, a bonding pad on the metal underlying layer with a wire bonded to the pad, and an insulative protection layer formed on the first main surface and surrounding the bonding pad. The bonding pad includes first and second conductive layers. The first conductive layer covers the metal underlying layer and is made of a metal having a lower ionization tendency than the metal underlying layer. The second conductive layer covers the first conductive layer and is made of a metal having a lower ionization tendency than the first conductive layer. The first and second conductive layers have respective peripheries held in close contact with the protection layer and covering a part of the protection layer.

A device for trapping ions includes: a substrate having a metal layer structure; and at least one ion trap configured to trap ions in a space over the substrate. The metal layer structure is a multi-layer metal structure that includes: a top metal layer having one or more electrodes forming part of the at least one ion trap; a redistribution metal layer having wiring for connecting the one or more electrodes; a first insulating layer arranged between the top metal layer and the redistribution layer and having one or more voids; and one or more connection elements arranged in the one or more voids that connect the wiring from the redistribution metal layer with the one or more electrodes in the top metal layer.

Disclosed herein is a package comprising a first redistribution layer (RDL) disposed on a first side of a first semiconductor substrate and a second RDL disposed on a second semiconductor substrate, wherein the first RDL is bonded to the second RDL. First conductive elements are disposed in the first RDL and the second RDL. First vias extend from one or more of the first conductive elements through the first semiconductor substrate to a second side of the first semiconductor substrate opposite the first side. First spacers are interposed between the first semiconductor substrate and the first vias and each extend from a respective one of the first conductive elements through the first semiconductor substrate.