A synthesizer circuit to generate a local oscillator carrier signal for a baseband signal includes a controlled oscillator comprising a phase lock loop and an oscillator configured to generate an oscillating signal. A pulling compensation circuit is configured to generate a correction signal for a present output of the phase locked loop using information on an error of the oscillating signal, information on a present sample of a baseband signal and a preceding correction signal for a preceding output of the phase locked loop.

A biased-transistor-module comprising: a module-input-terminal; a module-output-terminal; a reference-terminal; a module-supply-terminal configured to receive a supply voltage; a module-reference-voltage-terminal configured to receive a module reference voltage; a main-transistor having a main-control-terminal, a main-first-conduction-channel-terminal and a main-second-conduction-channel-terminal, wherein the main-first-conduction-channel-terminal is connected to the module-output-terminal, and the main-second-conduction-channel-terminal is connected to the reference-terminal, and the main-control-terminal is connected to an input-signal-node, wherein the input-signal-node is connected to the module-input-terminal; and a bias-circuit. The bias-circuit comprises: a first-bias-transistor; a first-bias-resistor; a second-bias-transistor; and a second-bias-resistor.

An apparatus includes a low noise amplifier (LNA) multiplexer configured to receive a plurality of radio frequency (RF) signals at a plurality of input terminals and to combine the plurality of RF signals into a combined RF signal that is output at an output terminal. The LNA multiplexer includes a plurality of input signal paths, and each input signal path is coupleable to a respective input terminal of the plurality of input terminals and is configured to receive a respective RF signal of the plurality of RF signals. The apparatus further includes an LNA demultiplexer configured to receive the combined RF signal at an input port coupled to the output terminal and to distribute the combined RF signal to a plurality of output ports, each output port of the plurality of output ports configured to output the combined RF signal to a respective downconverter of a plurality of downconverters.

An apparatus for providing a supply control signal for a supply unit, the supply unit being configured to provide a variable controlled power supply to the power amplifier. The apparatus includes a determination module configured to determine a deviation of a signal from at least one nominal value; and an adjustment module configured to provide the supply control signal after an adjustment based on the determined deviation.

Various aspects of the present disclosure generally relate to wireless communication. A wireless communication device may have an apparatus that aligns the non-linearity between transmit chains of the wireless communication device that are driven by the same digital port. The apparatus may adjust an amplification power out or an amplification saturated power to adjust a ratio between the amplification saturated power and the amplification power out for one or more transmit chains of the wireless communication device. The apparatus may adjust the ratios of transmit chains to align the ratios of the transmit chains for more consistent management of non-linear characteristics of the chain components. Numerous other aspects are described.

Circuits, devices and methods related to antenna tuner. In some embodiments, an antenna can be tuned by amplifying a signal for transmission by operating a transistor with a base current, and monitoring the base current. The method can further include adjusting an antenna tuner to thereby adjust an antenna load impedance presented to the amplified signal, with the adjustment being based on a variation of the monitored base current.

A distortion compensation device includes a first table, a second table, a calculating unit, a first updating unit, and a second updating unit. The first table holds a coefficient of a nonlinear term included in a filtering coefficient associated with an address other than a prescribed address obtained from the input signal x(n). The second table holds a coefficient of a linear term related to the prescribed address. The calculating unit calculates, based on the output signal, each of the update amounts of the coefficient of the nonlinear term and the coefficient of the linear term. The first updating unit updates each of the coefficients in the first table based on the update amount of the coefficient of the nonlinear term. The second updating unit updates each of the coefficients of the second table based on the update amount of the coefficient of the linear term.

A clamping circuit that may be used to provide efficient and effective voltage clamping in an RF front end. The clamping circuit comprises two series coupled signal path switches and a bypass switch coupled in parallel with the series coupled signal path switches. A diode is coupled from a point between the series coupled signal path switches to a reference potential. In addition, an output selection switch within an RF front end has integrated voltage clamping to more effectively clamp the output voltage from the RF front end. Additional output clamping circuits can be used at various places along a direct gain signal path, along an attenuated gain path and along a bypass path.

An amplification circuit includes: a power supply terminal that is connected to a power supply; a transistor that has a source terminal, a drain terminal, and a gate terminal to which a high-frequency signal is input; a transistor that has a source terminal that is connected to the drain terminal, a drain terminal that outputs a high-frequency signal, and a gate terminal that is grounded; a capacitor that is serially disposed on a second path that connects the gate terminal and the power supply terminal to each other; and a switch that is serially disposed on a first path or the second path. The drain terminal and the gate terminal are connected to each other via the switch and the capacitor.

A power amplifier output stage includes a first output array group having a first plurality of semiconductor devices, and a first loading adjustment module coupled to the first output array group. The first loading adjustment module is configured to adjust a loading of the first output array group to produce a first power dissipation value associated with the first output array group. The power amplifier output stage further includes a second output array group having a second plurality of semiconductor devices, and a second source loading adjustment module coupled to a second input of the second output array. The second source loading adjustment module is configured to adjust a source loading of the second output array group to produce a second power dissipation value associated with the second output array group, the first power dissipation value being different from the second power dissipation value.