The technology described in this document can be embodied in an audio power amplifier that includes a pair of switching devices, drive circuitry for driving the pair of switching devices to produce a signal, and an output filter to filter the signal from the pair of switching devices. The output filter is configured to provide the filtered signal to an audio load. The audio power amplifier includes a voltage feedback loop to provide a voltage of the filtered signal to a voltage controller of the audio power amplifier, and a current feedback loop to provide a current of the filtered signal to a current controller of the audio power amplifier.

A power amplifier arrangement (200) for amplifying an input signal to produce an output signal comprises a plurality N of amplifier sections (212, 213), a first input transmission line (221) comprising multiple segments and a first output transmission line (231) comprising multiple segments. Each amplifier section comprises one or more first transistors (T1) distributed along the first input transmission line (221) and the first output transmission line (231). Each amplifier section is configured to amplify a portion of the input signal to produce a portion of the output signal. A portion of the input signal is one of N portions of the input signal partitioned on any one or a combination of an amplitude basis and a time basis. The output signal is produced at an end of the first output transmission line (231) by building up N potions of the output signal from each amplifier section.

A class AB amplifier with improved DC gain. An amplifier includes an input stage and an output stage. The output stage is configured to amplify an output of the input stage. The output stage includes output transistors, class AB amplifier circuitry, minimum selector circuitry, and gain boost amplifier circuitry. The class AB amplifier circuitry includes a first transistor and a second transistor connected as a differential amplifier. The minimum selector circuitry is configured to control bias current in the output transistors by driving a control input of the first transistor. The gain boost amplifier circuitry is coupled to the class AB amplifier circuitry. The gain boost amplifier circuitry is configured to drive a common mode signal onto the control input of the first transistor and a control input of the second transistor, the common mode signal based on the output of the input stage.

Methods, circuits, and apparatuses that provide Buffer Amplifier, containing Amplifiers and Buffer Drivers, one or more of the following: ultra low power Buffer Amplifier, capable of having high gain, low noise, high speed, near rail-to-rail input-output voltage span, high sink-source current drive capability for an external load, and able to operate at low power supply voltages. Methods, circuits, and apparatuses that provide regulated cascode (RGC) current mirrors (CM) capable of operating at low power supply and having wide input-output voltage spans.

Methods, circuits, and apparatuses that provide Buffer Amplifier, containing Amplifiers and Buffer Drivers, one or more of the following: ultra low power Buffer Amplifier, capable of having high gain, low noise, high speed, near rail-to-rail input-output voltage span, high sink-source current drive capability for an external load, and able to operate at low power supply voltages. Methods, circuits, and apparatuses that provide regulated cascode (RGC) current mirrors (CM) capable of operating at low power supply and having wide input-output voltage spans.

An automated testing system comprises a high side switch circuit coupled to an input/output (I/O) connection, a low side switch circuit coupled to the I/O connection, a high side force amplifier (HFA) coupled to the high side switch, a low side force amplifier (LFA) coupled to the low side switch, an adjusting circuit coupled to the HFA and the LFA, and a control circuit configured to change the adjusting circuit to change control of current at the I/O connection from one of the HFA or LFA to the other of the HFA or LFA.

An active low-power termination circuit includes a first leg of a pair of transistors connected in series between the high supply level and ground, where the termination input is at a node between the transistors of the first node. A second leg uses a feed forward mechanism to control the voltage levels on the control gates of the transistors of the first leg. The second leg includes a second pair diode connected transistors, each of which is has its control gate connected to the control gate of the corresponding transistor in the first leg. A variable current source connected in series with the transistors of the second leg and is controlled by the output of a difference amplifier that has one input connect to an intermediate node of the second leg and a second input connected to a reference level intermediate to the high supply level and ground.

A line receiver comprising a switched capacitor circuit and a buffer is described. The buffer may be configured to receive, through the switched capacitor circuit, an analog signal. In response, the buffer may provide an output signal to a load, such as an analog-to-digital converter. The switched capacitor circuit may be controlled by a control circuitry, and may charge at least one capacitive element to a desired reference voltage. The reference voltage may be selected so as to bias the buffer with a desired DC current, and consequently, to provide a desired degree if linearity. The line receiver may further comprise a bias circuit configured to generate the reference voltage needed to bias the buffer with the desired DC current.

The present disclosure provides an amplifier circuit that includes one or more amplifier stages, each of the one or more amplifier stages including a complementary transistor configuration. The complementary transistor configuration includes an NMOS transistor and a PMOS transistor. The NMOS transistor is electrically coupled in parallel to the PMOS transistor. The amplifier circuit further includes an output amplifier stage electrically coupled to an output of the one or more amplifier stages, the output amplifier stage including a non-complementary transistor configuration including one or more NMOS transistors or PMOS transistors.

A class AB amplifier with improved DC gain. An amplifier includes an input stage and an output stage. The output stage is configured to amplify an output of the input stage. The output stage includes output transistors, class AB amplifier circuitry, minimum selector circuitry, and gain boost amplifier circuitry. The class AB amplifier circuitry includes a first transistor and a second transistor connected as a differential amplifier. The minimum selector circuitry is configured to control bias current in the output transistors by driving a control input of the first transistor. The gain boost amplifier circuitry is coupled to the class AB amplifier circuitry. The gain boost amplifier circuitry is configured to drive a common mode signal onto the control input of the first transistor and a control input of the second transistor, the common mode signal based on the output of the input stage.