A technology related to a power amplifier used in a wireless communication circuit is disclosed. A radio frequency (RF) power amplifier includes a plurality of unit differential amplifiers of which inputs are connected to a common input terminal and outputs are connected to a common adder, and having a gain of a weight of a corresponding bit of a binary gain control word. Each of the differential amplifiers may be configured as a complementary metal-oxide semiconductor (CMOS) differential cascode amplifier. In addition, the RF power amplifier may include a structure in which a plurality of attenuators of the same structure are cascade-connected so that an attenuation rate may be linearly and digitally controlled and an output of each attenuator is connected to an output adder through differential buffers of which turn-on and turn-off are controlled by a controller.

LNA circuitry includes an input node, and output node, a primary amplifier stage, a first ancillary amplifier stage, and an input gain selection switch. The primary amplifier stage is configured to provide a first gain response between a primary amplifier stage input node and a primary amplifier stage output node, wherein the primary amplifier stage input node is coupled to the input node and the primary amplifier stage output node is coupled to the output node. The first ancillary amplifier stage is configured to provide a second gain response between a first ancillary amplifier stage input node and a first ancillary amplifier stage output node, wherein the first ancillary amplifier stage output node is coupled to the primary amplifier stage output node. The input gain selection switch is coupled between the input node and the first ancillary amplifier stage input node.

The present invention is directed to electrical circuits and techniques thereof. More specifically, an embodiment of the present invention provides a variable gain amplifier that includes a first transistor and a second transistor whose gate terminals are coupled to a first input terminal. A first drain terminal of the first transistor and a first source terminal of the second transistor is coupled to a voltage gain control switch. There are other embodiments as well.

A variable gain amplifier and an electronic apparatus. The variable gain amplifier includes a first transconductance stage circuit and a second transconductance stage circuit, where the first transconductance stage circuit includes a first amplifying circuit and a second amplifying circuit, the second transconductance stage circuit includes a third amplifying circuit and a fourth amplifying circuit, the first amplifying circuit and the fourth amplifying circuit form a differential input pair, and the second amplifying circuit and the third amplifying circuit form a differential input pair, and where each amplifying circuit of the first amplifying circuit, the second amplifying circuit, the third amplifying circuit, and the fourth amplifying circuit includes a plurality of parallel transistors, and bias control of the plurality of transistors is independent of each other.

A method of controlling bandwidth and peaking over gain in a variable gain amplifier (VGA) device and structure therefor. The device includes at least three differential transistor pairs configured as a cross-coupled differential amplifier with differential input nodes, differential bias nodes, differential output nodes, a current source node, and two cross-coupling nodes. The cross-coupled differential amplifier includes a load resistor coupled to each of the differential output nodes and one of the cross-coupling nodes, and a load inductor coupled to the each of the cross-coupling nodes and a power supply rail. A current source is electrically coupled to the current source node. The cross-coupling configuration with the load resistance and inductance results in a lower bandwidth and lowered peaking at low gain compared to high gain. Further, the tap point into the inductor can be chosen as another variable to “tune” the bandwidth and peaking in a communication system.

Technologies are provided for variable gain amplifiers (VGAs). An example VGA includes a resistor ladder including resistor legs coupled to first and second resistors; first differential switches connected to the resistor ladder and second differential switches connected to output nodes, a transistor in each of the first differential switches being coupled to an first electrical line interconnecting the first resistors and a different transistor in each of the first differential switches being coupled to a second electrical line interconnecting the second resistors; third differential switches connected to the resistor ladder and fourth differential switches connected to the output nodes, a transistor in each of the third differential switches being coupled to the first electrical line and a different transistor in each of the fourth differential switches being coupled to the second electrical line; and a pair of transistors respectively connected to the first differential switches and the third differential switches.

A multi-gain LNA with inductive source degeneration is presented. The inductive source degeneration is provided via a tunable degeneration network that includes an inductor in parallel with one or more switchable shunting networks. Each shunting network includes a shunting capacitor that can selectively be coupled in parallel to the inductor. A capacitance of the shunting capacitor is calculated so that a combined impedance of the inductor and the shunting capacitor at a narrowband frequency of operation is effectively an inductance. The inductance is calculated according to a desired gain of the LNA. According to one aspect, the switchable shunting network includes a resistor in series connection with the shunting capacitor to provide broadband frequency response stability of the tunable degeneration network. According to another aspect, the LNA includes a plurality of selectable branches to further control gain of the LNA.

A transimpedance amplifier (TIA) circuit disclosed includes an input terminal, a first TIA circuit, a second TIA circuit, a field effect transistor (FET), and a gain control circuit. The first TIA circuit outputs a voltage signal from a first output in accordance with an input current received at a first input electrically connected to the input terminal. The second TIA circuit outputs a reference signal from a second output. The FET varies a resistance between a first current terminal and a second current terminal in accordance with a control signal applied to a control terminal. The first current terminal is electrically connected to the input terminal. The second current terminal is electrically connected to the second output of the second TIA circuit. The gain control circuit detects an amplitude of the voltage signal and generates the control signal according to a detection result of the amplitude.

An LNA having a plurality of paths, each of which can be controlled independently to achieve a gain mode. Each path includes at least an input FET and an output FET coupled in series. A gate of the output FET is controlled to set the gain of the LNA. Signals to be amplified are applied to the gate of the input FET. Additional stacked FETs are provided in series between the input FET and the output FET.

A variable gain amplifier circuit includes first and second input terminals, first and second output terminals, first and second transistors respectively having bases electrically connected to the first and second input terminals and having collectors electrically connected to the first and second output terminals, and a degeneration circuit connected between emitters of the first and second transistors. The degeneration circuit has first and second MOS transistors each having two current terminals connected in series between the emitters of the first and second transistors, series resistor circuits, first and second current sources, two resistive elements connected between the first and second current sources and gates of the first and second MOS transistors, and two resistive elements connected between the first and second current sources and two nodes of the series resistor circuits.