The present invention is directed electrical circuits. According to a specific embodiment, the present invention provides a variable gain amplifier that includes a first switch, which includes drain terminal coupled to an inductor. A second switch is configured in parallel to the inductor, and the resistance value of the second switch is adjustable in response to a control signal. There are other embodiments as well.

Analog multipliers can perform signal processing with approximate precision asynchronously (clock free) and with low power consumptions, which can be advantageous including in emerging mobile and portable artificial intelligence (AI) and machine learning (ML) applications near or at the edge and or near sensors. Based on low cost, mainstream, and purely digital Complementary-Metal-Oxide-Semiconductor (CMOS) manufacturing process, the present invention discloses embodiments of current-mode analog multipliers that can be utilized in multiply-accumulate (MAC) signal processing in end-application that require low cost, low power consumption, (clock free) and asynchronous operations.

Analog multipliers can perform signal processing with approximate precision asynchronously (clock free) and with low power consumptions, which can be advantageous including in emerging mobile and portable artificial intelligence (AI) and machine learning (ML) applications near or at the edge and or near sensors. Based on low cost, mainstream, and purely digital Complementary-Metal-Oxide-Semiconductor (CMOS) manufacturing process, the present invention discloses embodiments of current-mode analog multipliers that can be utilized in multiply-accumulate (MAC) signal processing in end-application that require low cost, low power consumption, (clock free) and asynchronous operations.

An active current source load of a fully differential amplifier which is converted into a transconductance (g.sub.m) component also at higher frequency by feed-forwarding input signals to their gates. With signal coupling to gate, unity gain bandwidth (UGB) of the amplifier increases by a factor of two. In addition to this, the signal is coupled to source as well to achieve three-fold UGB enhancement. Thus, the effective trans-conductance is g.sub.mp at dc and becomes g.sub.mp+(g.sub.mn.sub.gate+g.sub.mn.sub.src) at high frequency which triples the UGB when g.sub.mp=g.sub.mn.sub.gate/src.

Embodiments of a linear equalizer are disclosed. In an embodiment, a linear equalizer includes a plurality of input transistors, a plurality of gain control transistors and first and second impedance elements. The plurality of input transistors is connected to input terminals of the linear equalizer to receive input signals. The plurality of gain control transistors is connected between a supply voltage and the plurality of input transistors. The plurality of gain control transistors is also connected to gain control terminals to receive gain control signals. At least some of the gain control transistors are connected to output terminals of the linear equalizer to transmit output signals. The first and second impedance elements are connected between at least some of the input transistors and at least one fixed voltage. A peaking gain of the linear equalizer is defined by gain control signals applied to the gain control terminals.

According to one embodiment, a signal processing circuit includes a first voltage setting circuit that sets a reference voltage on an input side of an isolator, a variable gain amplifier circuit that amplifies an output signal of the isolator, a DC offset adjustment circuit that adjusts an offset of the variable gain amplifier circuit, a second voltage setting circuit that sets a reference voltage on an output side of the isolator, and a control circuit that controls the DC offset adjustment circuit in response to a result of comparison of an output voltage of the variable gain amplifier circuit with an output voltage of the second voltage setting circuit.

A variable gain amplifier includes a differential amplifier circuit having a pair of input terminals and a pair of output terminals, and a first variable attenuation circuit connected between at least one of the pair of input terminals and the pair of output terminals of the differential amplifier circuit and capable of switching a resistance value on the basis of a control signal which is input from the outside.

An offset compensated differential amplifier employing a multi-tan h circuit comprising differential pairs coupled in parallel to compensate for an offset voltage of the output voltage in the offset compensation calibration mode is disclosed. The differential pairs each include a compensation transistor coupled to the positive internal node and a reference transistor coupled to the negative internal node. Each compensation transistor receives the compensation control voltage and each reference transistor receives a different reference voltage. The multi-tan h circuit generates an offset compensation voltage on the positive and negative internal nodes based on a difference between the compensation control voltage and the different reference voltages. The multi-tan h circuit comprises a larger linear range than a hyperbolic tangent current transfer function of a single differential pair. The offset compensated differential amplifier provides offset compensation with improved linearity and a finer granularity compared to a conventional differential amplifier.

A variable-gain amplifier and a phased array system are provided. A variable-gain amplifier includes a cascode circuit comprising a first amplification transistor and a second amplification transistor array that are cascaded, the second amplification transistor array comprising a plurality of second amplification transistors connected in parallel and configured to output an adjustable current to an output matching network, the first amplification transistor is a common-source transistor, the plurality of second amplification transistors are common-gate transistors, or the cascode circuit is a common-emitter common-base circuit, the first amplification transistor is a common-emitter amplification circuit, and the second amplification transistor array is a common-base amplification circuit. The variable-gain amplifier further including a variable capacitor circuit coupled to the second amplification transistor array and coupled to the output matching network at first nodes.

An LNA having a plurality of paths, each of which can be controlled independently to achieve a gain mode. Each path includes at least an input FET and an output FET coupled in series. A gate of the output FET is controlled to set the gain of the LNA. Signals to be amplified are applied to the gate of the input FET. Additional stacked FETs are provided in series between the input FET and the output FET.