H10K59/1201

Method of manufacturing thin film transistor and display device including polishing capping layer coplanar with active layer

A thin film transistor includes an active layer including a first portion having a first thickness and a second portion having a second thickness greater than the first thickness, a capping layer filling a thickness difference between the first portion and the second portion and arranged on the first portion, a gate insulating layer arranged on the capping layer, a gate electrode on the active layer, wherein the gate insulating layer and the capping layer are disposed between the gate electrode and the active layer, and a source electrode and a drain electrode connected to the active layer.

Display device having some edges of cover plate that do not overlap with the underlying array substrate and method for manufacturing the same

A display device and a method for manufacturing a display device are provided. The display device includes an array substrate and a cover plate. The array substrate is a silicon-based organic light-emitting diode array substrate. An orthographic projection of the array substrate in a plane parallel to the array substrate covers an orthographic projection of the cover plate in the plane, the orthographic projection of the array substrate includes a plurality of edges, the orthographic projection of the cover plate includes a plurality of edges, the plurality of edges of the array substrate are in one-to-one correspondence to the plurality of edges of the cover plate. At least two edges of the orthographic projection of the array substrate do not overlap with corresponding edges of the orthographic projection of the cover plate and are located outside the orthographic projection of the cover plate.

LIGHT-EMITTING DISPLAY DEVICE AND METHOD OF MANUFACTURING THE SAME
20230232665 · 2023-07-20 · ·

A light-emitting display device can include a plurality of first electrodes over a substrate; a bank to overlap an area between the first electrodes and an edge of each of the first electrodes; a bank recess in the bank at the area between the first electrodes; a hard mask pattern to partially overlap the bank recess and to abut an upper part of the bank; an organic layer on the first electrodes and the bank, the organic layer being discontinuous between an upper part of the hard mask layer pattern and the bank recess; and a second electrode. Also, the bank can include a bank lower portion having a first height under the bank recess, a bank body portion around the bank recess, the bank body portion having an acute taper with respect to the substrate, and a bank overlap portion to overlap the plurality of first electrodes.

Organic light-emitting diode (OLED) display and method of manufacturing the same
11705068 · 2023-07-18 · ·

An organic light-emitting diode (OLED) display is disclosed. In one aspect, the OLED display includes a lower substrate including a display area and a non-display area surrounding the display area, wherein a plurality of pixels are formed in the display area. The OLED display also includes an embedded circuit formed in the configured to apply a plurality of signals to the pixels, and an initialization wiring formed in the non-display area and configured to apply an initialization voltage to each of the pixels. The initialization circuit is formed in a layer so as to at least partially overlap with the area of the embedded circuit.

METHOD OF MANUFACTURING DISPLAY PANEL AND DISPLAY PANEL MANUFACTURED BY THE SAME
20230232681 · 2023-07-20 ·

A method of manufacturing a display panel includes forming a circuit layer including a gate, a source, and a drain on a base substrate and forming a light emitting element layer on the circuit layer. The forming of the circuit layer includes sequentially forming a preliminary metal layer, a preliminary oxide layer comprising molybdenum and tantalum, and a preliminary capping layer which comprise a preliminary electrode layer, cleaning the preliminary electrode layer, forming a photoresist layer pattern on the preliminary electrode layer, etching the preliminary electrode layer, and removing the photoresist layer pattern. During the etching of the preliminary electrode layer, a ratio between a removal speed ER.sub.1 of the preliminary oxide layer and a removal speed ER.sub.2 of the preliminary metal layer satisfies Equation 1 to maintain a low reflection property


1≤ER.sub.2/ER.sub.1≤3.   [Equation 1]

Display device

A display device includes a first polyimide layer, a first silicon oxide layer located above and in direct contact with the first polyimide layer, an amorphous silicon layer located above and in direct contact with the first silicon oxide layer, a second polyimide layer located above and in direct contact with the amorphous silicon layer, a plurality of light-emitting elements located above the second polyimide layer, a transistor array located above the second polyimide layer, the transistor array being configured to control light emission of the plurality of light-emitting elements, a transparent conductive layer located between the transistor array and the second polyimide layer, and a second silicon oxide layer located between and in direct contact with the transparent conductive layer and the second polyimide layer.

Method for manufacturing display apparatus

A manufacturing method of a display apparatus including preparing a substrate, forming an amorphous silicon layer on the substrate, cleaning the amorphous silicon layer with hydrofluoric acid, crystallizing the amorphous silicon layer into a polycrystalline silicon layer, and forming a metal layer directly on the polycrystalline silicon layer.

Organic light-emitting display apparatus and method of manufacturing the same

An organic light-emitting display apparatus includes a pixel-defining layer configured to surround a plurality of pixels while exposing an emission area of the plurality of pixels on a substrate; and a spacer provided on the pixel-defining layer and configured to allow a mask to be placed on the spacer, the mask being arranged for deposition of an emission layer in the emission area, wherein a distance in a plane direction between the spacer and each of the plurality of pixels is within 1 μm. A color mixture between pixels may be prevented by suppressing the shadow phenomenon in deposition of an emission layer such that performance and reliability of the organic light-emitting display apparatus may be significantly improved.

Array substrate and manufacturing method thereof, three-dimensional display panel and display device

The present disclosure relates to an array substrate, a manufacturing method thereof, a three-dimensional display panel, and a display device. The array substrate includes a plurality of sub-pixels arranged in an array. Each sub-pixel includes a first composite region and a second composite region alternately arranged, as well as a substrate; a partition portion formed in the second composite region; a pixel electrode including a first composite electrode formed in the first composite region and a second composite electrode formed on the partition portion; an organic light emitting layer formed on a side of the pixel electrode away from the substrate; a pixel defining layer formed on the substrate provided around the organic light emitting layer; a common electrode having a polarity opposite to the pixel electrode formed on a side of organic light emitting layer away from the substrate; and a packaging layer.

Display device

A display device includes a substrate, a first semiconductor pattern on the substrate and including a semiconductor layer of a first transistor, a first gate insulator on the substrate, a first conductive layer on the first gate insulator and including a first gate electrode of the first transistor and a first electrode of the capacitor connected to the first gate electrode of the first transistor, a first interlayer dielectric on the first gate insulator, a second semiconductor pattern on the first interlayer dielectric and including a semiconductor layer of a second transistor and a second electrode of the capacitor, a second gate insulator on the first interlayer dielectric, a second conductive layer on the second gate insulator and including a gate electrode of the second transistor and a third semiconductor pattern between the second semiconductor pattern and any one of the first conductive layer and the second conductive layer.