A semiconductor device structure and method for manufacturing the same are provided. The semiconductor device structure includes a first substrate, a second substrate, and a hybrid bond structure. The second substrate is bonded to the first substrate by the hybrid bond structure. The hybrid bond structure includes a dielectric structure, a conductive structure. The dielectric structure defines an air gap therein.

A semiconductor device may include a peripheral circuit comprising a plurality of transistors, a cell array and a contact array positioned adjacent to each other over the peripheral circuit, a bonding pad for electrically connecting the peripheral circuit with the cell array and the contact array, the bonding pad comprising first and second portions, wherein the first portion has a first width and is in electrical connection with at least one transistor of the peripheral circuit, wherein the second portion has a second width that is less than the first width of the first portion, and wherein a bonding via electrically connecting the bonding pad with the contact array or the cell array extends partially inside the first portion of the bonding pad.

Representative implementations of techniques and devices are used to reduce or prevent conductive material diffusion into insulating or dielectric material of bonded substrates. Misaligned conductive structures can come into direct contact with a dielectric portion of the substrates due to overlap, especially while employing direct bonding techniques. A barrier interface that can inhibit the diffusion is disposed generally between the conductive material and the dielectric at the overlap.

Various embodiments of the present disclosure are directed towards a three-dimensional (3D) trench capacitor, as well as methods for forming the same. In some embodiments, a first substrate overlies a second substrate so a front side of the first substrate faces a front side of the second substrate. A first trench capacitor and a second trench capacitor extend respectively into the front sides of the first and second substrates. A plurality of wires and a plurality of vias are stacked between and electrically coupled to the first and second trench capacitors. A first through substrate via (TSV) extends through the first substrate from a back side of the first substrate, and the wires and the vias electrically couple the first TSV to the first and second trench capacitors. The first and second trench capacitors and the electrical coupling therebetween collectively define the 3D trench capacitor.

A semiconductor package includes: a plurality of semiconductor chips; a plurality of bonding pads between two of the plurality of semiconductor chips; a bonding insulating layer surrounding the plurality of bonding pads between the two of the plurality of semiconductor chips; and a void controller between the plurality of bonding pads, wherein the plurality of bonding pads are directly connected to the two of the plurality of semiconductor chips, wherein the bonding insulating layer is directly connected to the two of the plurality of semiconductor chips, wherein the void controller is a cavity defined by the bonding insulating layer, one of the plurality of semiconductor chips, and the bonding insulating layer, or the one of the plurality of semiconductor chips and the bonding insulating layer, and wherein the void controller is filled with a gas.

A microelectronic structure with through substrate vias (TSVs) and method for forming the same is disclosed. The microelectronic structure can include a bulk semiconductor with a via structure. The via structure can have a first and second conductive portion. The via structure can also have a barrier layer between the first conductive portion and the bulk semiconductor. The structure can have a second barrier layer between the first and second conductive portions. The second conductive portion can extend from the second barrier layer to the upper surface of the bulk semiconductor. The microelectronic structure containing TSVs is configured so that the microelectronic structure can be bonded to a second element or structure.

An integrated circuit package and the method of forming the same are provided. The integrated circuit package may include a first die. The first die may include a first semiconductor substrate, a first bonding layer over the first semiconductor substrate, and a first die connector in the first bonding layer. The first bonding layer may include a first portion including a first material and a second portion including a second material, wherein the first material is different from the second material. A surface of the first bonding layer may include a surface of the first portion, a surface of the second portion, and a surface of the first die connector.

A substrate bonding apparatus of the present disclosure includes a first chuck having a diameter larger than that of a first substrate; a deformation plate configured to support the first substrate, and is configured to have a variable shape on the first chuck; and a deformation unit between the first chuck and the deformation plate, wherein the deformation unit includes a main supporter that is deformable to press the deformation plate, the main supporter having a closed curve shape with a penetrating center.

The present description relates to a method of manufacturing an electronic circuit (30) comprising: a support (32), an assembly site (31) having a first surface protruding from said support intended to be assembled to an assembly site of another electronic circuit by a self-assembly method; and a peripheral area (39) around said assembly site, the assembly site (31) comprising at least one level, each level comprising conductive pads (34) and insulating posts (380) between the conductive pads, said manufacturing method comprising the forming of said at least one level of the assembly site, such that the edges, in at least one direction (X) of the main plane (XY), of each level of the assembly site and the locations, in the at least one direction (X), of the conductive pads and of the insulating posts of the same level are defined in a same photolithography step of said method.

Semiconductor devices having interconnect structures with vertically offset bonding surfaces, and associated systems and methods, are disclosed herein. In one embodiment, a semiconductor device includes a semiconductor substrate at least partially covered by a first dielectric material having an upper surface, and an interconnect structure extending therefrom. The interconnect structure can include a plurality of conductive elements, and a continuous region of a first insulating material at least partially between the plurality of conductive elements. The plurality of conductive elements and the continuous region can have coplanar end surfaces. The interconnect structure can further include a perimeter structure at least partially surrounding the plurality of conductive elements and the continuous region. The perimeter structure can have an uppermost surface that can be vertically offset from the upper surface of the first dielectric material and/or the coplanar end surfaces.