Semiconductor devices having interconnect structures with vertically offset bonding surfaces, and associated systems and methods, are disclosed herein. In one embodiment, a semiconductor device includes a semiconductor substrate at least partially covered by a first dielectric material having an upper surface, and an interconnect structure extending therefrom. The interconnect structure can include a plurality of conductive elements, and a continuous region of a first insulating material at least partially between the plurality of conductive elements. The plurality of conductive elements and the continuous region can have coplanar end surfaces. The interconnect structure can further include a perimeter structure at least partially surrounding the plurality of conductive elements and the continuous region. The perimeter structure can have an uppermost surface that can be vertically offset from the upper surface of the first dielectric material and/or the coplanar end surfaces.

A method for forming a semiconductor structure includes receiving a first die having a first interconnect structure and a first bonding layer over the first interconnect structure, and a second die having a second interconnect structure and a second bonding layer over the second interconnect structure; forming a recess indenting into the first bonding layer; and forming a positioning member on the second bonding layer. The method further includes bonding the second die over the first die; and disposing the positioning member into the recess. The positioning member includes dielectric, is surrounded by the first bonding layer, and is isolated from the first interconnect structure and the second interconnect structure.

An integrated circuit package module includes an integrated circuit package device including a contact element, and a bonding system formed on the integrated circuit package device. The bonding system includes a bonding system substrate and a bonding element formed in the bonding system substrate and conductively coupled to the contact element of the integrated circuit package device. The bonding element includes (a) a conduction component conductively connected to the contact element, the conduction component formed from a first metal having a first melting point, and (b) a bonding component formed from a second metal having a second melting point lower than the first melting point of the first metal.

In accordance with the disclosure, an inductor may be formed over a semiconductor substrate of one or both dies in a face-to-face die arrangement while reducing the parasitic capacitance between the inductor and the adjacent die. In disclosed embodiments, a semiconductor device may include a void (e.g., an air gap) between the inductor and the adjacent die to reduce the parasitic capacitance between the inductor and the adjacent die. The void may be formed in the die that includes the inductor and/or the adjacent die. In some respects, the void may be etched in interface layers (e.g., comprising bump pads and dielectric material) between the semiconductor dies, and may extend along the length of the inductor.

Semiconductor devices having interconnect structures with vertically offset bonding surfaces, and associated systems and methods, are disclosed herein. In one embodiment, a semiconductor device includes a semiconductor substrate at least partially covered by a first dielectric material having an upper surface, and an interconnect structure extending therefrom. The interconnect structure can include a plurality of conductive elements, and a continuous region of a first insulating material at least partially between the plurality of conductive elements. The plurality of conductive elements and the continuous region can have coplanar end surfaces. The interconnect structure can further include a perimeter structure at least partially surrounding the plurality of conductive elements and the continuous region. The perimeter structure can have an uppermost surface that can be vertically offset from the upper surface of the first dielectric material and/or the coplanar end surfaces.

The present disclosure relates to a method for forming a semiconductor device structure. The method includes forming a first semiconductor die and forming a second semiconductor die. The first semiconductor die includes a first metal layer, a first conductive via over the first metal layer, and a first conductive polymer liner surrounding the first conductive via. The second semiconductor die includes a second metal layer, a second conductive via over the second metal layer, and a second conductive polymer liner surrounding the second conductive via. The method also includes forming a conductive structure electrically connecting the first metal layer and the second metal layer by bonding the second semiconductor die to the first semiconductor die. The conductive structure is formed by the first conductive via, the first conductive polymer liner, the second conductive via, and the second conductive polymer liner.

A package structure includes a first dielectric layer, semiconductor device(s) attached to the first dielectric layer, and an embedding material applied to the first dielectric layer so as to embed the semiconductor device therein, the embedding material comprising one or more additional dielectric layers. Vias are formed through the first dielectric layer to the at least one semiconductor device, with metal interconnects formed in the vias to form electrical interconnections to the semiconductor device. Input/output (I/O) connections are located on one end of the package structure on one or more outward facing surfaces thereof to provide a second level connection to an external circuit. The package structure interfits with a connector on the external circuit to mount the package perpendicular to the external circuit, with the I/O connections being electrically connected to the connector to form the second level connection to the external circuit.

A semiconductor device having a three-dimensional structure includes a first wafer including a first bonding pad on one surface thereof; a second wafer including a second bonding pad, which is bonded to the first bonding pad, on one surface thereof bonded to the one surface of the first wafer; a plurality of anti-warpage grooves on the one surface of the first wafer, and laid out in a stripe shape; and a plurality of anti-warpage ribs on the one surface of the second wafer and coupled respectively to the plurality of anti-warpage grooves, and laid out in a stripe shape.

The present invention discloses an SOC PMUT suitable for high-density system integration, an array chip and a manufacturing method thereof. With the SOC PMUT suitable for high-density system integration, vertical stacking and monolithic integration of a SOC PMUT array with CMOS auxiliary circuits is realized by means of direct bonding of active wafers and a vertical multi-channel metal wiring structure; in addition, the extension to the package layer is implemented by means of TSVs, without any bonding mini-pad on the periphery of the array for communication with the CMOS. Thus, the bottleneck of metal interconnections in conventional ultrasonic transducers is overcome, the chip area occupied by metal interconnections in ultrasonic transducers is greatly reduced, the metal wiring length is reduced, thus the resulting adverse effects of an electrical parasitic effect on the performance of the ultrasonic transducer array are reduced.

The present description relates to a method of manufacturing an electronic circuit (30) comprising: a support (32), an assembly site (31) having a first surface protruding from said support intended to be assembled to an assembly site of another electronic circuit by a self-assembly method; and a peripheral area (39) around said assembly site, the assembly site (31) comprising at least one level, each level comprising conductive pads (34) and insulating posts (380) between the conductive pads, said manufacturing method comprising the forming of said at least one level of the assembly site, such that the edges, in at least one direction (X) of the main plane (XY), of each level of the assembly site and the locations, in the at least one direction (X), of the conductive pads and of the insulating posts of the same level are defined in a same photolithography step of said method.