A semiconductor device with an anti-pad peeling structure is disclosed. The semiconductor device includes: a semiconductor substrate including a Through Substrate Via (TSV); a dielectric layer on the semiconductor substrate and including a plurality of recesses therein; and a pad above the semiconductor substrate to cover a portion of the dielectric layer and extend to the recesses; wherein the pad extends to the plurality of recesses, and a plurality of contact points are confined in the recesses between the pad and the conductive layer, and each of the contact points is at least partially excluded from a boundary of the TSV when being seen from a top-down perspective.

A semiconductor device with an anti-pad peeling structure is disclosed. The semiconductor device includes: a semiconductor substrate including a Through Substrate Via (TSV); a dielectric layer on the semiconductor substrate and including a plurality of recesses therein; and a pad above the semiconductor substrate to cover a portion of the dielectric layer and extend to the recesses; wherein the pad extends to the plurality of recesses, and a plurality of contact points are confined in the recesses between the pad and the conductive layer, and each of the contact points is at least partially excluded from a boundary of the TSV when being seen from a top-down perspective.

Technologies are generally described related to three-dimensional integration of integrated circuits (ICs) with spacing for heat dissipation. According to some examples, a self-aligned silicide may be formed in a temporary silicon layer and removed subsequent to bonding of the wafers to achieve improved contact between the combined ICs and enhanced heat dissipation through added spacing between the ICs.

A semiconductor device includes an insulation base material, a wiring layer, a via, and a semiconductor element. The insulation base material includes an insulating layer including an adhesive agent layer formed on one surface of the insulating layer. The wiring layer is formed on the one surface of the adhesive agent layer. The via is separately formed from the wiring layer and penetrates through the insulating layer and the adhesive agent layer, to be connected with the wiring layer. The semiconductor element is connected, via a sintered material, with another end of the via on an opposite side of one end of the via, the one end being connected with the wiring layer, on another surface of the insulating layer.

The present application discloses a semiconductor package structure and a packaging method. The semiconductor package structure includes a ceramic base and a lower package body. A crystal sheet is disposed in a groove at an upper surface of the ceramic base. The lower package body includes a first encapsulation layer which encapsulates a semiconductor chip and a second encapsulation layer which encapsulates a wiring layer. An active surface of the semiconductor chip is located inside the first encapsulation layer and is electrically coupled to the wiring layer. The ceramic base and the lower package body according to the present disclosure may be produced separately and then assembled. The package body may be produced in batches and then diced, which increases production efficiency and greatly reduces manufacturing costs. It also helps relieve mechanical stress, ensuring structural stability.

The present application belongs to the field of packaging technology, and particularly relates to a packaging structure for an RF front-end module. Through the interaction of the support structure and the first adhesive part arranged on the substrate, a cavity structure is formed between the first filter chip and the first surface of the substrate. Moreover, the first adhesive part does not require excessive area coverage, allowing for material savings. This design ensures the formation of a cavity between the filter chip and the substrate while maintaining cost efficiency, and it also improves the reliability of the packaging structure of an RF front-end module.

A semiconductor package includes a redistribution structure including redistribution vias extending from redistribution layers into an insulating layer, a plurality of semiconductor chips stacked on the redistribution structure, a molded layer between the redistribution structure and the plurality of semiconductor chips, connection wires electrically connecting corresponding connection pads and redistribution vias, and connection bumps below the redistribution structure. The connection wires include a first portion extending from each of the connection pads at a first inclination angle for a bottom surface of the molded layer, and a second portion extending from the first portion at a second inclination angle, narrower than the first inclination angle for the bottom surface of the molded layer. The second portion has an end surface in contact with corresponding redistribution vias, and each of the redistribution vias has a top surface in contact with the end surface of the second portion.