According to one aspect of the present disclosure, a terahertz device is provided. The terahertz device includes a semiconductor substrate, a terahertz element, and a first rectifying element. The terahertz element is disposed on the semiconductor substrate. The first rectifying element is electrically connected to the terahertz element in parallel.

An apparatus and method for reducing the volume of a resource allocation information message in a broadband wireless communication system are provided. The method includes transmitting a message including information indicating a periodicity of an uplink control channel for an initial network entry; and receiving an uplink signal for the initial network entry through the uplink control channel.

A switching power supply module includes a power inductor which includes a magnetic core and L-shaped metal end electrodes and a switching power supply chip which includes a packaging body, a bare chip and a bottom bonding pad of the bare chip; the L-shaped metal end electrode includes a first electrode part which is welded at 90 to the magnetic core and a second electrode part which extends in parallel from the first electrode part to the middle of the magnetic core and is perpendicular to the first electrode part; the bare chip and the packaging body are embedded between the first, the second electrode part and the magnetic core; the bottom bonding pad abuts between the two second electrode parts and is insulated from the second electrode part, and the weld face of the bottom bonding pad is flush with that of the second electrode part.

A semiconductor device is presented. The semiconductor device comprises a semiconductor body coupled to a first load terminal and to a second load terminal and configured to carry a load current between the first load terminal and the second load terminal. The first load terminal comprises a contiguous metal layer coupled to the semiconductor body; and at least one metal island arranged on top of and in contact with the contiguous metal layer and configured to be contacted by an end of a bond wire and to receive at least a part of the load current by means of the bond wire, wherein the contiguous metal layer and the metal island are composed of the same metal.

A first semiconductor die is provided, which includes a first substrate, first semiconductor devices, first interconnect-level dielectric material layers, first metal interconnect structures, and first bonding pads. A second semiconductor die is provided, which includes a semiconductor-on-insulator (SOI) substrate, second semiconductor devices, second interconnect-level dielectric material layers, second metal interconnect structures, and second bonding pads. The second bonding pads are bonded to the first bonding pads. A bulk substrate layer of the SOI substrate is removed exposing an insulating material layer of the SOI substrate, which may be retained or also removed. An external bonding pad is electrically connected to a node of the second semiconductor devices.

A method includes bonding a first wafer to a second wafer, with a first plurality of dielectric layers in the first wafer and a second plurality of dielectric layers in the second wafer bonded between a first substrate of the first wafer and a second substrate in the second wafer. A first opening is formed in the first substrate, and the first plurality of dielectric layers and the second wafer are etched through the first opening to form a second opening. A metal pad in the second plurality of dielectric layers is exposed to the second opening. A conductive plug is formed extending into the first and the second openings.

A bonding wire for a semiconductor device, characterized in that the bonding wire includes a Cu alloy core material and a Pd coating layer formed on a surface of the Cu alloy core material, the bonding wire contains an element that provides bonding reliability in a high-temperature environment, and a strength ratio defined by the following Equation (1) is 1.1 to 1.6:
Strength ratio=ultimate strength/0.2% offset yield strength.(1)

A semiconductor device including a transistor having high reliability is provided. The semiconductor device includes a transistor. The transistor includes first and second gate electrodes, a source electrode, a drain electrode, first to third oxides, first and second barrier films, and first and second gate insulators. The first barrier film is located over the source electrode, the second barrier film is located over the drain electrode, and the first and second barrier films each have a function of blocking oxygen and impurities such as hydrogen.

A method of generating a wire loop profile in connection with a semiconductor package is provided. The method includes the steps of: (a) providing package data related to the semiconductor package; and (b) creating a loop profile of a wire loop of the semiconductor package, the loop profile including a tolerance band along at least a portion of a length of the wire loop.

A method includes forming a metal layer extending into openings of a dielectric layer to contact a first metal pad and a second metal pad, and bonding a bottom terminal of a component device to the metal layer. The metal layer has a first portion directly underlying and bonded to the component device. A raised via is formed on the metal layer, and the metal layer has a second portion directly underlying the raised via. The metal layer is etched to separate the first portion and the second portion of the metal layer from each other. The method further includes coating the raised via and the component device in a dielectric layer, revealing the raised via and a top terminal of the component device, and forming a redistribution line connecting the raised via to the top terminal.