A wiring-buried glass substrate includes a glass substrate and a first wiring. The glass substrate includes a first surface, a second surface perpendicular to the first surface, and a third surface facing the first surface. The first wiring includes a first pillar portion and a first beam portion. The first pillar portion extends in a first direction perpendicular to the first surface of the glass substrate. The first beam portion is connected to a first surface of the first pillar portion and extends to a second direction perpendicular to a second surface of the glass substrate. The first wiring is buried in the glass substrate. The first surface of the first beam portion is exposed from a third surface of the glass substrate.

A method of fabricating a contact hole and a fuse hole includes providing a dielectric layer. A conductive pad and a fuse are disposed within the dielectric layer. Then, a first mask is formed to cover the dielectric layer. Later, a first removing process is performed by taking the first mask as a mask to remove part the dielectric layer to form a first trench. The conductive pad is disposed directly under the first trench and does not expose through the first trench. Subsequently, the first mask is removed. After that, a second mask is formed to cover the dielectric layer. Then, a second removing process is performed to remove the dielectric layer directly under the first trench to form a contact hole and to remove the dielectric layer directly above the fuse by taking the second mask as a mask to form a fuse hole.

Disclosed is a method of fabricating a semiconductor image sensor device. The method includes providing a substrate having a pixel region, a periphery region, and a bonding pad region. The substrate further has a first side and a second side opposite the first side. The pixel region contains radiation-sensing regions. The method further includes forming a bonding pad in the bonding pad region; and forming light-blocking structures over the second side of the substrate, at least in the pixel region, after the bonding pad has been formed.

Provided is a semiconductor device capable of reducing a mounting area. A semiconductor device (100) includes a semiconductor element (50) and a control element (150) arranged on a front surface (50a) of the semiconductor element (50). The semiconductor element (50) includes a semiconductor substrate (SB) including a first region AR1 and a second region AR2 adjacent to each other, a first MOS transistor (Tr1) provided is the first region (AR1), and a second MOS transistor (Tr2) provided in the second region (AR2). A first drain region (3a) of the first MOS transistor (Tr1) is connected to a second drain region (3b) of the second MOS transistor (Tr2). The control element (150) turns on and off the first MOS transistor (Tr1) and the second MOS transistor (Tr2).

A chip part includes a substrate, an element formed on the substrate, and an electrode formed on the substrate. A recess and/or projection expressing information related to the element is formed at a peripheral edge portion of the substrate.

A semiconductor device has a first semiconductor die including a first protection circuit. A second semiconductor die including a second protection circuit is disposed over the first semiconductor die. A portion of the first semiconductor die and second semiconductor die is removed to reduce die thickness. An interconnect structure is formed to commonly connect the first protection circuit and second protection circuit. A transient condition incident to the interconnect structure is collectively discharged through the first protection circuit and second protection circuit. Any number of semiconductor die with protection circuits can be stacked and interconnected via the interconnect structure to increase the ESD current discharge capability. The die stacking can be achieved by disposing a first semiconductor wafer over a second semiconductor wafer and then singulating the wafers. Alternatively, die-to-wafer or die-to-die assembly is used.

A circuit element is formed on a substrate made of a compound semiconductor. A bonding pad is disposed on the circuit element so as to at least partially overlap the circuit element. The bonding pad includes a first metal film and a second metal film formed on the first metal film. A metal material of the second metal film has a higher Young's modulus than a metal material of the first metal film.

To improve the reliability of a semiconductor device. The semiconductor device includes a plurality of wiring layers formed on a semiconductor substrate, a pad formed on an uppermost wiring layer of the plurality of wiring layers, a surface protection film which includes an opening on the pad and is made of an inorganic insulating film, a rewiring formed on the surface protection film; a pad electrode formed on the rewiring, and a wire connected to the pad electrode. The rewiring includes a pad electrode mounting portion on which the pad electrode is mounted, a connection portion which is connected to the pad, and an extended wiring portion which couples the pad electrode mounting portion and the connection portion, and the pad electrode mounting portion has a rectangular shape when seen in a plan view.

A conductive polymer shielding layer covering insulating layer formed on an integrated-circuit die is provided and a method thereof. The method comprises die attaching, wire bonding, back etching, insulation molding, partial cutting, conductive material/polymer coating, and singulation.

Embodiments of packaged semiconductor devices and methods of making thereof are provided herein, which include a semiconductor die having a plurality of pads on an active side; a dummy die having a plurality of openings that extend from a first major surface to a second major surface opposite the first major surface, wherein the plurality of openings are aligned with the plurality of pads; and a silicone-based glue attaching the dummy die to the active side of the semiconductor die, wherein a plurality of bondable surfaces of the semiconductor die are exposed through the plurality of openings of the dummy die.