An integrated circuit package can contain a semiconductor die and provide electrical connections between the semiconductor die and additional electronic components. The integrated circuit package can reduce stress placed on the semiconductor die due to movement of the integrated circuit package due to, for example, temperature changes and/or moisture levels. The integrated circuit package can at least partially mechanically isolate the semiconductor die from the integrated circuit package.

The present disclosure provides a redistribution layer (RDL) structure, a semiconductor device and manufacturing method thereof. The semiconductor device comprising an RDL structure that may include a substrate, a first conductive layer, a reinforcement layer and, and a second conductive layer. The first conductive layer may be formed on the substrate and has a first bond pad area. The reinforcement layer may be formed on a surface of the first conductive layer facing away from the substrate and located in the first bond pad area. The second conductive layer may be formed on the reinforcement layer and an area of the first conductive layer not covered by the reinforcement layer. The reinforcement layer has a material strength greater than those of the first conductive layer and the second conductive layer.

An embodiment of an IC is provided. The IC includes a memory, a controller, an intrusion detector and a memory clear circuit. The memory is configured to store sensitive data. The controller is configured to access the memory. The intrusion detector is configured to detect whether an intrusion event is present in response to an input signal. The memory clear circuit is configured to clear the sensitive data of the memory when the intrusion detector detects the intrusion event.

A semiconductor device includes: a first semiconductor chip having a first pad and a second pad, a depression being formed in the second pad; an organic insulating film provided on the first semiconductor chip, the organic insulating film covering the depression and not covering at least a portion of the first pad; and a redistribution layer having a lower portion connected to the first pad and an upper portion disposed on the organic insulating film.

Method and arrangement for assembling one or more microchips (415; 615; 715; 815; 915; 1015) into one or more holes (422; 722), respectively, in a substrate surface (421; 721) of a separate receiving substrate (420; 720; 820; 1020). The holes (422; 722) of the substrate is for microchip insertion out-of-plane in relation to said substrate surface. Each of said microchips is provided with a ferromagnetic layer (213; 613) of ferromagnetic material. The microchips are placed (503) on said substrate surface (421; 721) and it is applied and moved (504) one or more magnetic fields affecting said ferromagnetic layer (213; 613) of each microchip such that the microchips thereby become out-of-plane oriented in relation to said substrate surface (421; 721) and move over the substrate surface (421; 721) until assembled into said holes (422; 722).

A method for preparing a semiconductor device includes providing an integrated circuit die having a bond pad. The bond pad includes aluminum (Al). The method also includes etching a top portion of the bond pad to form a recess, and bonding a wire bond to the recess in the bond pad. The wire bond includes copper (Cu).

A switching power supply module includes a power inductor which includes a magnetic core and L-shaped metal end electrodes and a switching power supply chip which includes a packaging body, a bare chip and a bottom bonding pad of the bare chip; the L-shaped metal end electrode includes a first electrode part which is welded at 90° to the magnetic core and a second electrode part which extends in parallel from the first electrode part to the middle of the magnetic core and is perpendicular to the first electrode part; the bare chip and the packaging body are embedded between the first, the second electrode part and the magnetic core; the bottom bonding pad abuts between the two second electrode parts and is insulated from the second electrode part, and the weld face of the bottom bonding pad is flush with that of the second electrode part.

A performance of a semiconductor device is improved. The semiconductor device includes a semiconductor chip, and a clip mounted on the semiconductor chip via a silver paste. Here, the semiconductor chip includes a passivation film having an opening, a source pad of a main transistor having a portion exposed from the passivation film at the opening, and a wall portion provided on the passivation film so as to surround the source pad in a plan view. At this time, a whole of the portion (exposed surface) of the source pad, which is exposed from the passivation film, is covered with the silver paste. Further, in the plan view, the silver paste connecting the source pad with the clip is positioned inside of an area surrounded by the wall portion, without overflowing.

A semiconductor package according to the exemplary embodiments of the disclosure includes a base substrate including a base bonding pad, a first semiconductor chip disposed on the base substrate, a first adhesive layer provided under the first semiconductor chip, a first bonding pad provided in a bonding region on an upper surface of the first semiconductor chip, a first bonding wire interconnecting the base bonding pad and the first bonding pad, and a crack preventer provided in a first region at the upper surface of the first semiconductor chip. The crack preventer includes dummy pads provided at opposite sides of the first region and a dummy wire interconnecting the dummy pads.

This semiconductor device is provided with: a substrate which has, on a principal surface thereof, an input unit for inputting an alternating current power from the exterior, a ground connection unit for connecting to ground formed on the exterior, an output unit for outputting a post-adjustment direct current power to the exterior, and a semiconductor layer; a first Schottky barrier diode formed in a first region of the semiconductor layer so that a cathode electrode is connected to the input unit and so that an anode electrode is connected to the ground connection unit; a second Schottky barrier diode formed in a second region of the semiconductor layer so that a cathode electrode is connected to the output unit and so that an anode electrode is connected to the input unit; and a third Schottky barrier diode formed in a third region of the semiconductor layer so that a cathode electrode is connected to the output unit and so that an anode electrode is connected to the ground connection unit.