A step of forming a connecting member configured to electrically connect a first conductive line and a second conductive line includes a phase of perforating a laminate from a first semiconductor wafer to form a plurality of connection holes that reach the second conductive line and a phase of filling the plurality of penetrating connection holes with a conductive material to form conductive sections in contact with the second conductive line.

A circuit element is formed on a substrate made of a compound semiconductor. A bonding pad is disposed on the circuit element so as to at least partially overlap the circuit element. The bonding pad includes a first metal film and a second metal film formed on the first metal film. A metal material of the second metal film has a higher Young's modulus than a metal material of the first metal film.

A device with pillar-shaped components, includes a substrate; a wiring layer disposed on the substrate; and pillar-shaped components disposed on any of the substrate and the wiring layer, each of the pillar-shaped components having a bottom part connected to the substrate and/or the wiring layer, a top part opposed to the bottom part, and a lateral face part extending from the bottom part and connected to the top part; wherein each of the pillar-shaped components includes a first pillar-shaped part formed by plating, a second pillar-shaped part formed on the first pillar-shaped part by plating, and a ring-like projection part formed on the lateral face part to project outward and extend in a circumferential direction, and to be in a position higher than a joint position between the first pillar-shaped part and the second pillar-shaped part.

To protect the insulating film so that crack is not produced in the insulating film even when stress is applied to the semiconductor device. A manufacturing method of a semiconductor device is provided, including: forming an insulating film above a semiconductor substrate; forming, in the insulating film, one or more openings that expose the semiconductor substrate; forming a tungsten portion deposited in the openings and above the insulating film; thinning the tungsten portion on condition that the tungsten portion remains in at least part of a region above the insulating film; and forming an upper electrode above the tungsten portion.

A method and structure suitable for, e.g., improving high voltage breakdown reliability of a microelectronic device such as a capacitor usable for galvanic isolation of two circuits. A metal plate having a top surface and a side surface is located over a first dielectric layer. A second dielectric layer of a second different material is located over the first metal plate. A dielectric structure of the first material is located over the side surface of the metal plate and over the surface of the first dielectric layer.

A semiconductor device includes a bonding pad that includes a base portion having a base layer. A bond wire or clip is bonded to a bonding region of a main surface of the bonding pad. A supplemental structure is in direct contact with the base portion next to the bonding region. A specific heat capacity of the supplemental structure is higher than a specific heat capacity of the base layer.

A semiconductor device includes a substrate having a cell region and a circuit region, an upper wiring layer on the substrate, and a redistribution wiring layer on the upper wiring layer. The upper wiring layer includes a secondary uppermost wiring in the circuit region and an uppermost wiring on the secondary uppermost wiring. The uppermost wiring includes an uppermost chip pad electrically connected to the secondary uppermost wiring. At least a portion of the uppermost chip pad in the cell region. The redistribution wiring layer includes a redistribution wiring electrically connected to the uppermost chip pad. At least a portion of the redistribution wiring serving as a landing pad connected to an external connector.

A light emitting device can include a light emitting structure including a p-GaN based semiconductor layer, an active layer having multiple quantum wells, and an n-GaN based semiconductor layer; a p-electrode and an n-electrode electrically connecting with the light emitting structure, respectively, wherein the n-electrode has a plurality of layers; a first passivation layer including a first portion contacting a portion of the n-electrode, a second portion vertically overlapped with the p-electrode, and a third portion that extends outside of outermost side surfaces of the light emitting structure; a phosphor layer disposed on a top surface of the light emitting structure; and a second passivation layer including a first portion disposed between the phosphor layer and the top surface of the light emitting structure, and a second portion disposed on the outermost side surfaces of the light emitting structure, in which the phosphor layer includes a pattern to bond a wire with a p-pad on a portion of the p-electrode, the second portion of the second passivation layer extends toward the third portion of the first passivation and contacts the third portion of the first passivation layer, and the first passivation layer includes an opening on the n-GaN based semiconductor layer such that the opening accommodates at least a portion of the n-electrode.

A method of fabricating a contact hole and a fuse hole includes providing a dielectric layer. A conductive pad and a fuse are disposed within the dielectric layer. Then, a first mask is formed to cover the dielectric layer. Later, a first removing process is performed by taking the first mask as a mask to remove part the dielectric layer to form a first trench. The conductive pad is disposed directly under the first trench and does not expose through the first trench. Subsequently, the first mask is removed. After that, a second mask is formed to cover the dielectric layer. Then, a second removing process is performed to remove the dielectric layer directly under the first trench to form a contact hole and to remove the dielectric layer directly above the fuse by taking the second mask as a mask to form a fuse hole.

A method of generating a wire loop profile in connection with a semiconductor package is provided. The method includes the steps of: (a) providing package data related to the semiconductor package; and (b) creating a loop profile of a wire loop of the semiconductor package, the loop profile including a tolerance band along at least a portion of a length of the wire loop.