A disclosed circuit arrangement includes a support structure having first and second posts. Electrically conductive round wire has a round cross-section, and a first portion is wrapped at least partially around the first post. A second portion of the wire extends in a straight line from a point on a perimeter of the first post to a point on a perimeter of the second post, and a third portion of the wire is wrapped at least partially around the second post. The second portion of the round wire defines one or more bond sites. An electronic device is electrically connected to the round wire at one of the one or more bond sites.

The present invention: makes it possible to improve the reliability of a semiconductor device; and provides a method of manufacturing the semiconductor device comprising the steps of (a) providing a semiconductor wafer having a pad electrode, a first conductive layer comprised of copper, a photoresist film, and a second conductive layer comprised of gold, (b) forming a protective film comprised of iodine on the surface of the second conductive layer, (c) removing the photoresist film, (d) irradiating the protective film with argon ions and removing the protective film, and (e) bringing a part of a bonding wire into contact with the surface of the second conductive layer.

The present disclosure relates to a solid-state imaging apparatus, a manufacturing method of the same and an electronic device which can make an apparatus size further smaller.

A solid-state imaging apparatus includes: a laminate of a first structure in which a pixel array unit in which pixels that perform photoelectric conversion are two-dimensionally arranged is formed and a second structure in which an output circuit unit configured to output pixel signals output from the pixels to an outside of an apparatus is formed. The output circuit unit, a first through hole via which penetrates through a semiconductor substrate constituting part of the second structure, and an external terminal for signal output connected to the outside of the apparatus are disposed below the pixel array unit of the first structure. The present disclosure can be applied, for example, to a solid-state imaging apparatus or the like.

An integrated circuit has a substrate and an interconnect region disposed on the substrate. The interconnect region includes a plurality of interconnect levels. Each interconnect level includes interconnects in dielectric material. The integrated circuit includes a graphitic via in the interconnect region. The graphitic via vertically connects a first interconnect in a first interconnect level to a second interconnect in a second, higher, interconnect level. The graphitic via includes a cohered nanoparticle film of nanoparticles in which adjacent nanoparticles cohere to each other, and a layer of graphitic material disposed on the cohered nanoparticle film. The nanoparticles include one or more metals suitable for catalysis of the graphitic material. The cohered nanoparticle film is formed by a method which includes an additive process. The graphitic via is electrically coupled to an active component of the integrated circuit.

In various embodiments, a method is provided. The method includes forming a metallization layer above at least one first region of a substrate. After forming the metallization layer at least one second region of the substrate is free of the metallization layer. The method further includes forming a barrier layer above the at least one first region of the substrate and above the at least one second region of the substrate. The barrier layer in the at least one first region of the substrate directly adjoins the metallization layer. The method further includes removing the barrier layer in the at least one first region of the substrate by drive-in of the barrier layer into the metallization layer.

A circuit element is formed on a substrate made of a compound semiconductor. A bonding pad is disposed on the circuit element so as to at least partially overlap the circuit element. The bonding pad includes a first metal film and a second metal film formed on the first metal film. A metal material of the second metal film has a higher Young's modulus than a metal material of the first metal film.

Some embodiments relate to a bond pad structure of an integrated circuit (IC). The bond structure includes a bond pad and an intervening metal layer positioned below the bond pad. The intervening metal layer has a first face and a second face. A first via layer is in contact with the first face of intervening metal layer. The first via layer has a first via pattern. The bond structure also includes a second via layer in contact with the second face of the intervening metal layer. The second via layer has a second via pattern that is different than first via pattern. The second via pattern includes a first group of elongated vias extending in parallel with one another in a first direction and a second group of vias in between the first group of elongated vias. The second group of vias extend in a second direction orthogonal to the first direction.

A method for sputtering an aluminum layer on a surface of a semiconductor device is presented. The method includes three sputtering steps for depositing the aluminum layer, where each sputtering step includes at least one sputtering parameter that is different from a corresponding sputtering parameter of another sputtering step. The surface of the semiconductor device includes a dielectric layer having a plurality of openings formed through the dielectric layer.

The object of the present invention is to suppress cracks in the interlayer insulating film attributed to growth of Cu crystal grains. The semiconductor device (101) includes a source region (5), an interlayer insulating film (7) made of silicon oxide, having an opening portion, and formed on the source region (5), a Cu electrode (1) electrically connected to the source region (5) through the opening portion of the interlayer insulating film (7) and an end portion thereof is located on the interlayer insulating film (7) inside an end portion of the interlayer insulating film (7), and a stress relieving layer (13) formed between the Cu electrode (1) and the interlayer insulating film (7), made of a material having a higher fracture toughness value than the interlayer insulating film (7), and extending from the inside to the outside of the end portion of the Cu electrode (1).

To provide a semiconductor device having improved reliability. A method of manufacturing the semiconductor device includes connecting a wire comprised of copper with a conductive layer formed on the pad electrode of a semiconductor chip, heat treating the semiconductor chip, and then sealing the semiconductor chip and the wire with a resin.