A method of manufacturing a semiconductor device includes providing a semiconductor substrate, forming, over a main surface the semiconductor substrate, a first insulating film, forming, over the first insulating film, an Al-containing conductive film containing aluminum as a main component, patterning the Al-containing conductive film to form a pad, forming, over the first insulating film, a second insulating film to cover the pad therewith, forming an opening in the second insulating film, and electrically coupling a copper wire to the pad exposed from the opening.

An isolation system, isolation device, and Integrated Circuit are disclosed. The isolation system is described to include an integrated circuit chip having a first capacitive plate, a second capacitive plate positioned with respect to the first capacitive plate to enable a capacitive coupling therebetween, an enhanced isolation layer positioned between the first capacitive the second capacitive plate that facilitates an electrical isolation between the first capacitive plate and the second capacitive plate, a first bonding wire that is in electrical communication with the second capacitive plate, and an isolation trench that at least partially circumscribes the first capacitive plate and is positioned between the first capacitive plate and the first bonding wire.

A solid-state imaging apparatus includes: a solid-state imaging device photoelectrically converting light taken by a lens; and a light shielding member shielding part of light incident on the solid-state imaging device from the lens, wherein an angle made between an edge surface of the light shielding member and an optical axis direction of the lens is larger than an incident angle of light to be incident on an edge portion of the light shielding member.

A method for remapping an extracted die is provided. The method includes one or more of removing an extracted die from a previous integrated circuit package, the extracted die including a plurality of original bond pads having locations that do not correspond to desired pin assignments of a new package base and bonding an interposer to the extracted die. The interposer includes first bond pads configured to receive new bond wires from the plurality of original bond pads and second bond pads corresponding to desired pin assignments of the new package base, each individually electrically coupled to one of the first bond pads and configured to receive new bond wires from package leads or downbonds of the new package base.

A semiconductor device including a first material layer adjacent to a second material layer, a first via passing through the first material layer and extending into the second material layer, and a second via extending into the first material layer, where along a common cross section parallel to an interface between the two material layers, the first via has a cross section larger than that of the second via.

In various embodiments, a method is provided. The method includes forming a metallization layer above at least one first region of a substrate. After forming the metallization layer at least one second region of the substrate is free of the metallization layer. The method further includes forming a barrier layer above the at least one first region of the substrate and above the at least one second region of the substrate. The barrier layer in the at least one first region of the substrate directly adjoins the metallization layer. The method further includes removing the barrier layer in the at least one first region of the substrate by drive-in of the barrier layer into the metallization layer.

A remapped extracted die is provided. The remapped extracted die includes an extracted die removed from a previous integrated circuit package. The extracted die includes a plurality of original bond pads having locations that do not correspond to desired pin assignments of a new package base and an interposer, bonded to the extracted die. The interposer includes first bond pads configured to receive new bond wires from the plurality of original bond pads, and second bond pads corresponding to desired pin assignments of the new package base, each individually electrically coupled to one of the first bond pads and configured to receive new bond wires from package leads or downbonds of the new package base.

An electronic isolation device is formed on a monolithic substrate and includes a plurality of passive isolation components. The isolation components are formed in three metal levels. The first metal level is separated from the monolithic substrate by an inorganic PMD layer. The second metal level is separated from the first metal level by a layer of silicon dioxide. The third metal level is separated from the second metal level by at least 20 microns of polyimide or PBO. The isolation components include bondpads on the third metal level for connections to other devices. A dielectric layer is formed over the third metal level, exposing the bondpads. The isolation device contains no transistors.

An electronic isolation device is formed on a monolithic substrate and includes a plurality of passive isolation components. The isolation components are formed in three metal levels. The first metal level is separated from the monolithic substrate by an inorganic PMD layer. The second metal level is separated from the first metal level by a layer of silicon dioxide. The third metal level is separated from the second metal level by at least 20 microns of polyimide or PBO. The isolation components include bondpads on the third metal level for connections to other devices. A dielectric layer is formed over the third metal level, exposing the bondpads. The isolation device contains no transistors.

A technique is provided that can prevent cracking of a protective film in the uppermost layer of a semiconductor device and improve the reliability of the semiconductor device. Bonding pads formed over a principal surface of a semiconductor chip are in a rectangular shape, and an opening is formed in a protective film over each bonding pad in such a manner that an overlapping width of the protective film in a wire bonding region of each bonding pad becomes wider than an overlapping width of the protective film in a probe region of each bonding pad.