A chip package including a first substrate having an upper surface, a lower surface and a sidewall is provided. A sensing region or device region and a conducting pad are adjacent to the upper surface. A through-hole penetrates the first substrate. A redistribution layer extends from the lower surface into the through-hole and is electrically connected to the conducting pad. The redistribution layer further laterally extends from the lower surface to protrude from the sidewall. A method for forming the chip package is also provided.

A semiconductor device is disclosed including at least first and second vertically stacked and interconnected semiconductor packages. Signal communication between the second semiconductor package and a host device occurs through the first semiconductor package.

A method of generating a wire loop profile in connection with a semiconductor package is provided. The method includes the steps of: (a) providing package data related to the semiconductor package; and (b) creating a loop profile of a wire loop of the semiconductor package, the loop profile including a tolerance band along at least a portion of a length of the wire loop.

A microelectronic device is formed by thinning a substrate of the microelectronic device from a die attach surface of the substrate, and forming a copper-containing layer on the die attach surface of the substrate. A protective metal layer is formed on the copper-containing layer. Subsequently, the copper-containing layer is attached to a package member having a package die mount area. The protective metal layer may optionally be removed prior to attaching the copper-containing layer to the package member. Alternatively, the protective metal layer may be left on the copper-containing layer when the copper-containing layer is attached to the package member. A structure formed by the method is also disclosed.

The present disclosure relates to an image pickup device and an electronic apparatus that enable further downsizing of device size. The device includes: a first structural body and a second structural body that are layered, the first structural body including a pixel array unit, the second structural body including an input/output circuit unit, and a signal processing circuit; a first through-via, a signal output external terminal, a second through-via, and a signal input external terminal that are arranged below the pixel array, the first through-via penetrating through a semiconductor substrate constituting a part of the second structural body, the second through-via penetrating through the semiconductor substrate; a substrate connected to the signal output external terminal and the signal input external terminal; and a circuit board connected to a first surface of the substrate. The present disclosure can be applied to, for example, the image pickup device, and the like.

An electronic device includes a leadframe having a die pad and leads. A die having an active side is attached to the die pad. The die further includes a dielectric layer deposited on a side of the die opposite that of the active side and an die attach film deposited on the dielectric layer. Wire bonds are attached from the active side of the die to the leads. A critical signal wire bond is attached from the active side of the die to the die pad. A mold compound encapsulates the die, the wire bonds, the critical signal wire bond, and a portion of the leadframe. A stacked formation of the die, the dielectric layer, and the die attach film form a capacitor that filters noise from a critical signal carried by the critical signal wire bond.

Integrated circuits having copper bonding structures with silicon carbon nitride passivation layers and methods for making the same are provided. In an exemplary embodiment, an integrated circuit includes a substrate and a copper bonding structure having a contact surface. The copper bonding structure overlies the substrate. A passivation layer formed of silicon carbon nitride is disposed on the contact surface.

An optical module includes a semiconductor optical device in which an active layer located at one side, an electrode located at the same side, and a mirror that reflects light toward the side opposite the electrode are monolithically integrated, a sub-mount having one surface on which a first wiring pattern is formed, a substrate in which an optical waveguide and a grating coupler are formed in a surface layer of the substrate, a spacer having an upper surface on which a second wiring pattern is formed, and a wire. The sub-mount is mounted on the spacer. The first wiring pattern on the sub-mount faces part of the second wiring pattern on the spacer and is electrically connected thereto. The second wiring pattern on the spacer includes a pad being disposed in a region exposed from the sub-mount and being bonded to the wire.

A solid-state imaging apparatus includes: a solid-state imaging device photoelectrically converting light taken by a lens; and a light shielding member shielding part of light incident on the solid-state imaging device from the lens, wherein an angle made between an edge surface of the light shielding member and an optical axis direction of the lens is larger than an incident angle of light to be incident on an edge portion of the light shielding member.

A technique is provided that can prevent cracking of a protective film in the uppermost layer of a semiconductor device and improve the reliability of the semiconductor device. Bonding pads formed over a principal surface of a semiconductor chip are in a rectangular shape, and an opening is formed in a protective film over each bonding pad in such a manner that an overlapping width of the protective film in a wire bonding region of each bonding pad becomes wider than an overlapping width of the protective film in a probe region of each bonding pad.