Various embodiments relate to an optoelectronic component including: an electronic circuit structure including an electronic circuit and a metallization structure disposed over the electronic circuit, the metallization structure including one or more contact pads electrically connected to the electronic circuit; and an optoelectronic structure disposed over the metallization structure, the optoelectronic structure including at least one electrode structure being in direct contact with the one or more contact pads, wherein the electrode structure includes an electroless plated electrically conductive material.

An imaging apparatus that forms an image of a light beam transmitted through an imaging lens on an imaging element includes a laminated material that is provided on the imaging element, the light beam being transmitted through the laminated material, the laminated material being provided at a position at which an end portion of an upper surface of the laminated material allows an outermost light beam out of light beams to be transmitted therethrough, the light beams entering a pixel in an outer end portion of the imaging element in an effective pixel area, the position having a width Hopt.

The invention provides a semiconductor structure. The semiconductor structure includes a substrate. A first passivation layer is disposed on the substrate. A conductive pad is disposed on the first passivation layer. A second passivation layer is disposed on the first passivation layer. A passive device is disposed on the conductive pad, passing through the second passivation layer. An organic solderability preservative film covers the passive device.

A solid-state imaging apparatus includes: a solid-state imaging device photoelectrically converting light taken by a lens; and a light shielding member shielding part of light incident on the solid-state imaging device from the lens, wherein an angle made between an edge surface of the light shielding member and an optical axis direction of the lens is larger than an incident angle of light to be incident on an edge portion of the light shielding member.

A method of manufacturing an electronic device may include: forming at least one electronic component in a substrate; forming a contact pad in electrical contact with the at least one electronic component; wherein forming the contact pad includes: forming a first layer over the substrate; planarizing the first layer to form a planarized surface of the first layer; and forming a second layer over the planarized surface, wherein the second layer has a lower porosity than the first layer.

A solid-state imaging apparatus includes: a solid-state imaging device photoelectrically converting light taken by a lens; and a light shielding member shielding part of light incident on the solid-state imaging device from the lens, wherein an angle made between an edge surface of the light shielding member and an optical axis direction of the lens is larger than an incident angle of light to be incident on an edge portion of the light shielding member.

A nitride semiconductor light emitting element 1 includes a second conductivity type nitride semiconductor layer which is formed above thea first conductivity type nitride semiconductor layer, a first electrode 17a which is formed on a first region of the second conductivity type nitride semiconductor layer with a first current non-injection layer 13a in between, a first current diffusing layer 14a which is formed between the first current non-injection layer 13a and the first electrode 17a, a second electrode 17b which is formed on a second region of the second conductivity type nitride semiconductor layer with a second current non-injection layer 13b in between, a second current diffusing layer 14b which is formed on the second region and on the second current non-injection layer 13b, and an extending portion 17c which extends from the first electrode 17a and reaches the exposed first conductivity type nitride semiconductor layer.

A semiconductor device is presented. The semiconductor device comprises a semiconductor body coupled to a first load terminal and to a second load terminal and configured to carry a load current between the first load terminal and the second load terminal. The first load terminal comprises a contiguous metal layer coupled to the semiconductor body; and at least one metal island arranged on top of and in contact with the contiguous metal layer and configured to be contacted by an end of a bond wire and to receive at least a part of the load current by means of the bond wire, wherein the contiguous metal layer and the metal island are composed of the same metal.

An isolation device for isolating a first signal of a first circuit from a second circuit disclosed. The isolation device may have a substrate and a plurality of metal layers disposed on the substrate. The isolation device comprises a first plate that is electrically coupled to the first circuit, and a second plate that is electrically coupled to the second circuit. The first plate is configured to transmit the first signal from to a second plate that is electrically isolated from the first plate. The first plate and the second plate is surrounded by an isolation material. The isolation device further comprises at least one trench that extend at least partially through the isolation material in a direction that is substantially perpendicular to the first plate and the second plate. The at least one trench may circumscribe one of the first plate and the second plate.

An isolation system, isolation device, and Integrated Circuit are disclosed. The isolation system is described to include an integrated circuit chip having a first capacitive plate, a second capacitive plate positioned with respect to the first capacitive plate to enable a capacitive coupling therebetween, an enhanced isolation layer positioned between the first capacitive the second capacitive plate that facilitates an electrical isolation between the first capacitive plate and the second capacitive plate, a first bonding wire that is in electrical communication with the second capacitive plate, and an isolation trench that at least partially circumscribes the first capacitive plate and is positioned between the first capacitive plate and the first bonding wire.