A semiconductor package includes a semiconductor device including a plurality of signal pads and a plurality of auxiliary pads which are alternatively arranged in a predetermined direction, and a package board including a plurality of signal bond fingers, a plurality of first power supply voltage bond fingers, and a plurality of second power supply voltage bond fingers. The signal pads are connected respectively to the signal bond fingers by first wires. The first power supply voltage bond fingers and the second power supply voltage bond fingers are connected respectively to the auxiliary pads by second wires. The first wires are disposed between those of the second wires which are connected to the first power supply voltage bond fingers and those of the second wires which are connected to the second power supply voltage bond fingers.

High voltage integrated circuit capacitors are disclosed. In an example arrangement. A capacitor structure includes a semiconductor substrate; a bottom plate having a conductive layer overlying the semiconductor substrate; a capacitor dielectric layer deposited overlying at least a portion of the bottom plate and having a first thickness greater than about 6 um in a first region; a sloped transition region in the capacitor dielectric at an edge of the first region, the sloped transition region having an upper surface with a slope of greater than 5 degrees from a horizontal plane and extending from the first region to a second region of the capacitor dielectric layer having a second thickness lower than the first thickness; and a top plate conductor formed overlying at least a portion of the capacitor dielectric layer in the first region. Methods and additional apparatus arrangements are disclosed.

Reliability of a semiconductor device is improved. A slope is provided on a side face of an interconnection trench in sectional view in an interconnection width direction of a redistribution layer. The maximum opening width of the interconnection trench in the interconnection width direction is larger than the maximum interconnection width of the redistribution layer in the interconnection width direction, and the interconnection trench is provided so as to encapsulate the redistribution layer in plan view.

To provide a semiconductor device having improved reliability. The semiconductor device is equipped with a first polyimide film, rewirings formed over the first polyimide film, first and second dummy patterns formed over the first polyimide film, a second polyimide film that covers the rewirings and the dummy patterns, and an opening portion that exposes a portion of the rewirings in the second polyimide film. The first dummy pattern is, in plan view, comprised of a closed pattern surrounding the rewirings while having a space therebetween.

A semiconductor package is provided. The semiconductor package may include at least one semiconductor chip including a contact pad configured to conduct a current, a conductor element, wherein the conductor element is arranged laterally overlapping the contact pad and with a distance to the contact pad, at least one electrically conductive spacer, a first adhesive system configured to electrically and mechanically connect the at least one electrically conductive spacer with the contact pad, and a second adhesive system configured to electrically and mechanically connect the at least one electrically conductive spacer with the conductor element, wherein the conductor element is electrically conductively connected to a clip or is at least part of a clip, and wherein the spacer is configured to electrically conductively connect the contact pad with the laterally overlapping portion of the conductor element.

In an embodiment, a semiconductor device includes a semiconductor body having a first major surface, a second major surface opposing the first major surface and at least one transistor device structure, a source pad and a gate pad arranged on the first major surface, a drain pad and at least one further contact pad coupled to a further device structure. The drain pad and the at least one further contact pad are arranged on the second major surface.

In plan view, an electrode pad of a semiconductor chip includes: a first region that contains a center of an exposed portion of the electrode pad; a second region that is located around the first region; and a third region that is located around the first region and that is located between the first region and the second region. Here, a first groove that separates a plurality of semiconductor elements formed in a semiconductor substrate from each other is formed in the semiconductor substrate. The semiconductor substrate includes: a fourth region that overlaps with the third region but not overlaps with each of the first region and the second region, and a fifth region that overlaps with the first region but not overlaps with the third region. And, the first groove is formed in the semiconductor substrate at the fifth region but not at the fourth region.

A fingerprint sensing device comprising sensing circuitry comprising a plurality of sensing elements, each sensing element comprising a sensing structure arranged in a sensing plane and facing a surface of the capacitive fingerprint sensing device, each of the sensing elements being configured to provide a signal indicative of an electromagnetic coupling between the sensing structure and a finger placed on the surface of the fingerprint sensing device; and a plurality of connection pads electrically connected to the sensing circuitry for providing an electrical connection between the sensing circuitry and readout circuitry, wherein each of the connection pads is separately recessed in relation to the sensing plane such that each connection pad has a floor in a floor plane, and wherein each connection pad is separated from an adjacent connection pad through a portion of the sensing device being elevated in relation to the floor plane.

A microelectronic device contains a high voltage component having a high voltage node and a low voltage node. The high voltage node is isolated from the low voltage node by a main dielectric between the high voltage node and low voltage elements at a surface of the substrate of the microelectronic device. A lower-bandgap dielectric layer is disposed between the high voltage node and the main dielectric. The lower-bandgap dielectric layer contains at least one sub-layer with a bandgap energy less than a bandgap energy of the main dielectric. The lower-bandgap dielectric layer extends beyond the high voltage node continuously around the high voltage node. The lower-bandgap dielectric layer has an isolation break surrounding the high voltage node at a distance of at least twice the thickness of the lower-bandgap dielectric layer from the high voltage node.

An optical module includes a semiconductor optical device in which an active layer located at one side, an electrode located at the same side, and a mirror that reflects light toward the side opposite the electrode are monolithically integrated, a sub-mount having one surface on which a first wiring pattern is formed, a substrate in which an optical waveguide and a grating coupler are formed in a surface layer of the substrate, a spacer having an upper surface on which a second wiring pattern is formed, and a wire. The sub-mount is mounted on the spacer. The first wiring pattern on the sub-mount faces part of the second wiring pattern on the spacer and is electrically connected thereto. The second wiring pattern on the spacer includes a pad being disposed in a region exposed from the sub-mount and being bonded to the wire.