A semiconductor device includes a chip having a first main surface which serves as a device surface and a second main surface which serves as a non-device surface, and a first conductivity type drift gradient region formed in the chip, and having a concentration profile in which an impurity concentration of an end portion on the first main surface side is lower than an impurity concentration of an end portion on the second main surface side.

A semiconductor device includes a chip having a principal surface, a pn-junction portion extending in a horizontal direction along the principal surface inside the chip, a trench insulating structure formed in the principal surface such that the trench insulating structure penetrates through the pn-junction portion, and demarcating a diode region in the chip, a barrier forming region formed in a surface layer portion of the principal surface in the diode region, and a metal layer located on the principal surface such that the metal layer covers the barrier forming region in the diode region, and forming a Schottky-junction portion with the barrier forming region.

A method for forming a graphene layer on a semiconductor substrate, a semiconductor diode utilizing the method for graphene layer formation, and an optoelectronic semiconductor device also utilizing the method for graphene layer formation are provided. An example method for disposing a graphene layer on a semiconductor substrate may include depositing a metal catalyst layer on a top surface of the semiconductor substrate and patterning the metal catalyst layer, such that one or more portions of the top surface of the semiconductor substrate are covered by one or more metal catalyst layer structures. The method may further include facilitating a graphene growth process on an exposed surface of the one or more metal catalyst layer structures, wherein the graphene growth process forms the graphene layer on the exposed surfaces of the one or more metal catalyst layer structures.

A semiconductor structure is provided. The semiconductor structure includes a substrate, an epitaxial layer, multiple field plate structures, multiple shielding layers, an upper electrode layer, and a lower electrode layer. The epitaxial layer is disposed on the substrate. The field plate structures include a first field plate structure and a second field plate structure respectively disposed in a first unit and a second unit of the semiconductor structure. The shielding layers are disposed between the bottom portions of the field plate structures and the epitaxial layer. The upper electrode layer covers the field plate structures. The upper electrode layer is separated from the epitaxial layer in the first unit and is in direct contact with the epitaxial layer in the second unit. The lower electrode layer is disposed under the substrate and opposite to the epitaxial layer.

A method for manufacturing a SiC-based electronic device, that includes implanting, at a front side of a solid body of SiC having a conductivity of N type, dopant species of P type, thus forming an implanted region that extends in depth in the solid body starting from the front side and has a top surface co-planar with said front side; and generating a laser beam directed towards the implanted region in order to generate heating of the implanted region at temperatures comprised between 1500 C. and 2600 C. so as to form an ohmic contact region including one or more carbon-rich layers, for example graphene and/or graphite layers, in the implanted region and, simultaneously, activation of the dopant species of P type.

A number of Monolithic Microwave Integrated Circuit (MMIC) devices including combinations of PIN and Schottky diodes, with integrated passive electrical components fabricated and electrically connected among them, are described herein, along with new process techniques for forming the MMIC devices. In one example, a monolithic semiconductor includes a substrate, a plurality of layers of semiconductor materials over the substrate, Schottky and Ohmic contacts on a first subset of the plurality of layers for a Schottky diode, and PIN diode Ohmic contacts on a second subset of the plurality of layers for a PIN diode. The device can also include an etch stop layer between the first subset of the plurality of layers and the second subset of the plurality of layers. The etch stop layer facilitates selective etching and isolation of the Schottky diode from the PIN diode by consecutive etchings.

A number of Monolithic Microwave Integrated Circuit (MMIC) devices including combinations of PIN and Schottky diodes, with integrated passive electrical components fabricated and electrically connected among them, are described herein, along with new process techniques for forming the MMIC devices. In one example, a monolithic semiconductor includes a substrate, a plurality of layers of semiconductor materials over the substrate, Schottky and Ohmic contacts on a first subset of the plurality of layers for a Schottky diode, and PIN diode Ohmic contacts on a second subset of the plurality of layers for a PIN diode. The device can also include an etch stop layer between the first subset of the plurality of layers and the second subset of the plurality of layers. The etch stop layer facilitates selective etching and isolation of the Schottky diode from the PIN diode by consecutive etchings.

A semiconductor device, including: a semiconductor substrate including a first-conductivity-type region at a first main surface; a second-conductivity-type region selectively provided at the first main surface and extending in a first direction parallel to the first main surface; a first electrode provided at the first main surface, forming a Schottky junction with the first-conductivity-type region and being in contact with the second-conductivity-type region; and a second electrode provided on a second main surface. The first-conductivity-type region and the second-conductivity-type region includes a plurality of upper surface portions that are aligned in both the first direction and a second direction parallel to the first main surface and perpendicular to the first direction. Each of the upper surface portions forms a first step with another upper surface portion adjacent thereto in the second direction, and forms a second or third step with another upper surface portion adjacent thereto in the first direction.

A semiconductor device includes an SiC semiconductor layer which has a first main surface on one side and a second main surface on the other side, a semiconductor element which is formed in the first main surface, a raised portion group which includes a plurality of raised portions formed at intervals from each other at the second main surface and has a first portion in which some of the raised portions among the plurality of raised portions overlap each other in a first direction view as viewed in a first direction which is one of the plane directions of the second main surface, and an electrode which is formed on the second main surface and connected to the raised portion group.

A semiconductor device includes a semiconductor layer that is of a first conductivity type, a body region of a second conductivity type, a source region to be separated inwardly from an outer edge of the body region, a drain region formed on a surface of the semiconductor layer so as to be separated from the body region in a first direction orthogonal to a thickness direction of the semiconductor layer, a gate insulating layer formed on a portion of the surface of the semiconductor layer between the source region and the drain region in the first direction, a gate electrode that is formed on the gate insulating layer, an exposed region that is formed in the body region at a different position from the source region and in which the semiconductor layer is exposed, and a metal layer that forms a Schottky junction with the exposed region.