A method used in forming an array of memory cells comprises forming a vertical stack comprising transistor material directly above and directly against a first capacitor electrode material. A mask is used to subtractively etch both the transistor material and thereafter the first capacitor electrode material to form a plurality of pillars that individually comprise the transistor material and the first capacitor electrode material. Capacitors are formed that individually comprise the first capacitor electrode material of individual of the pillars. Vertical transistors are formed above the capacitors that individually comprise the transistor material of the individual pillars. Other aspects and embodiments are disclosed, including structure independent of method.

The present disclosure provides a method of manufacturing a semiconductor device. The method includes steps of creating at least one trench in a substrate; depositing a conductive material to partially fill the trench; and forming an insulative piece in the trench and extending into the conductive material.

The present application discloses a semiconductor device and a method for fabricating the semiconductor device. The semiconductor device includes a substrate; a first contact positioned on the substrate; a first assistance feature including: a bottom portion positioned in the first contact, and a capping portion positioned on the bottom portion and on a top surface of the first contact; a second contact positioned on the substrate and separated from the first contact; and a second assistance feature positioned on the second contact. The first assistance feature and the second assistance feature include germanium or silicon germanium.

An apparatus that includes a semiconductor substrate having first and second gate trenches arranged in parallel and extending in a first direction, and first and second gate electrodes embedded in the first and second gate trenches, respectively, via a gate insulating film. Each of the first and second gate electrodes includes a first conductive film located at a bottom of the respective first and second gate trenches and a second conductive film stacked on the first conductive film. The second conductive film included in a first portion of the second gate electrode is thinner than the second conductive film included in a first portion of the first gate electrode which is arranged adjacently to the first portion of the second gate electrode in a second direction crossing to the first direction. The second conductive film is lower in work function than the first conductive film.