An electronic device including a two-dimensional material is provided. The electronic device may include a substrate; a metal layer on a partial region of the substrate; a two-dimensional material layer over the metal layer and an upper surface of the substrate; and an insertion layer between the metal layer and the two-dimensional material layer.

An electronic device including a two-dimensional material is provided. The electronic device may include a substrate; a metal layer on a partial region of the substrate; a two-dimensional material layer over the metal layer and an upper surface of the substrate; and an insertion layer between the metal layer and the two-dimensional material layer.

Methods and apparatus for forming a patterned layer of material on a substrate. In one arrangement, a selected portion of a surface of a substrate is irradiated during a deposition process. The irradiation locally drives the deposition process in the selected portion to form a patterned layer of material in a pattern defined by the selected portion. A bias voltage of alternating polarity is applied to the substrate during the irradiation to periodically drive secondary electrons generated inside the substrate by the irradiation towards the surface in the selected portion.

Semiconductor devices and methods of forming the same are provided. A method includes providing a workpiece having a semiconductor structure; depositing a two-dimensional (2D) material layer over the semiconductor structure; forming a source feature and a drain feature electrically connected to the semiconductor structure and the 2D material layer, wherein the source feature and drain feature include a semiconductor material; and forming a gate structure over the two-dimensional material layer and interposed between the source feature and the drain feature. The gate structure, the source feature, the drain feature, the semiconductor structure and the 2D material layer are configured to form a field-effect transistor. The semiconductor structure and the 2D material layer function, respectively, as a first channel and a second channel between the source feature and the drain feature.

The present disclosure relates to a gate all around (GAA) device made based on a GAA transistor structure that comprises a stack of multiple semiconductor channel layers and one or more first gate layers alternatingly arranged along a first direction. Each channel layer is encapsulated by a gate dielectric layer, and each first gate layer is arranged between two channel layers following another. The GAA transistor structure further comprises two second gate layers sandwiching the stack in a second direction and connected to the first gate layers. Each first gate layer is made of a first work function metal structure and each second gate layer is made of a second work function metal structure that is different from the first work function metal structure. Each first gate layer has a first thickness and each second gate layer has a second thickness larger than the first thickness.

A semiconductor storage device includes a plurality of memory cells aligned in first and second directions, each memory cell extends in a third direction and includes a MOS transistor and a capacitor, the MOS transistor includes a first insulating layer that extends in the third direction, a semiconductor layer that extends in the third direction to surround a side surface of the first insulating layer and is formed of a two-dimensional material, and a gate electrode that is provided outside the semiconductor layer, the capacitor includes a first electrode, a second electrode, and a capacitor material layer extending in the third direction, the first electrode surrounds a side surface of the second electrode, the capacitor material layer is provided between the first electrode and the second electrode, and the first electrode is in contact with a first end portion of the semiconductor layer in the third direction.

A semiconductor device including high-integrated memory cells and a method for fabricating the semiconductor device is provided. The semiconductor device may include a first sub-cell array including first memory cells that are vertically stacked; a second sub-cell array including second memory cells that are horizontally adjacent to the first memory cells, the second memory cells being vertically stacked; a linear opening horizontally extending between the first sub-cell array and the second sub-cell array; and a vertical conductive line formed in the linear opening, the vertical conductive line being electrically coupled to the first memory cells and the second memory cells that are horizontally adjacent to each other.