A chip package assembly includes a first high-power chip, a second low-power chip, a thermal cooling device and a heterogeneous thermal interface material (HTIM). The thermal cooling device may overlie the first chip and the second chip. The HTIM includes a first thermal interface material (TIM) and a second TIM. The first TIM overlies the first chip, and the second TIM overlies the second chip. The first TIM includes a material that has a first thermal conductivity and a first modulus of elasticity. The first TIM can reflow when the first die reaches a first TIM reflow temperature. The second TIM comprises at least a polymer material. The second TIM has a second modulus of elasticity that is greater than the first modulus of elasticity and a second thermal conductivity that is less than the first thermal conductivity.

Various embodiments of the teachings herein include a sintered power electronic module with a first plane and a second plane different from the first plane. An example comprises: a first substrate with a first metallization arranged on the first plane; a second substrate with a second metallization arranged on the second plane; a switchable die having a first power terminal and a second power terminal, the die arranged between the first substrate and the second substrate; and a surface area of all the sintered connections of the first plane is between 90 and 110% of a surface area of all the sintered connections of the second plane. The first power terminal of the die is joined to the first metallization via a sintered connection in the first plane and the second power terminal is joined to the second metallization via a sintered connection in the second plane.

The present invention discloses an elastic heat spreader for chip packaging, a packaging structure and a packaging method. The heat spreader includes a top cover plate and a side cover plate that extends outward along an edge of the top cover plate, wherein the top cover plate is configured to be placed on a chip, and at least a partial region of the side cover plate is an elastic member; and the elastic member at least enables the side cover plate to be telescopic in a direction perpendicular to the top cover plate. According to the present invention, a following problem is solved: delamination between the heat spreader and a substrate as well as the chip due to stress generated by different thermal expansion coefficients of the substrate, the heat spreader and the chip in a packaging process of a large-size product.

A semiconductor package includes a package substrate, a first semiconductor chip mounted on the package substrate and that includes a first semiconductor substrate that includes through electrodes, and a second semiconductor chip disposed on the first semiconductor chip and that includes a second semiconductor substrate that includes an active surface and an inactive surface. The second semiconductor chip further includes a plurality of isolated heat dissipation fins that extend in a vertical direction from the inactive surface.

A semiconductor package includes a package substrate, a first semiconductor chip and a second semiconductor chip sequentially stacked on the package substrate, the first semiconductor chip and the second semiconductor chip being disposed in a form of an offset stack structure, and the second semiconductor chip including an overhang further protruding beyond a side surface of the first semiconductor chip in a first horizontal direction, an adhesive member disposed on a lower surface of the second semiconductor chip, the adhesive member including an extension extending to a lower level than an upper surface of the first semiconductor chip. The extension contacts the side surface of the first semiconductor chip, and overlaps with at least a portion of the overhang in a vertical direction.

A lead frame includes a base comprising a bearing surface for bearing a chip. The bearing surface includes a soldering region, with a solder layer arranged in the soldering region. The solder layer is configured for fixing the chip on the bearing surface. The lead frame includes a groove provided on the bearing surface in a thickness direction of the base. The groove is located outside the soldering region and surrounds at least part of the soldering region along the outer periphery of the soldering region for receiving solder paste overflowed from the soldering region. A depth of the groove is based on a thickness of the base. A packaging structure including the lead frame and a packaging method using the lead frame are also provided.

Electronic structures and methods of assembly are described in which a lid with pocket sidewalls is mounted on a routing substrate such that the pocket sidewalls laterally surround an electronic component and provide a barrier to outflow of the thermal interface layer outside of the pocket sidewalls, and in particular a thermal interface layer including a liquid metal film.

A method includes attaching a permeable plate to a metal lid, with the permeable plate including a metallic material, and dispensing a liquid-metal-comprising media to a first package component. The first package component is over and bonded to a second package component. The liquid-metal-comprising media includes a liquid metal therein. The method further includes attaching the metal lid to the second package component. During the attaching, the liquid-metal-comprising media migrates into the permeable plate to form a composite thermal interface material.

A package structure and a method of manufacturing a package structure are provided. The package structure includes a first substrate, a first electronic component, a second substrate and a second electronic component. The first electronic component is disposed over a first through hole of the first substrate. The first electronic component is electrically connected to a first patterned circuit layer of the first substrate through an extending portion of the first patterned circuit layer extending beyond a sidewall of the first through hole. The second electronic component is disposed over a second through hole of the second substrate. The second electronic component is electrically connected to a second patterned circuit layer of the second substrate through an inner extending portion of the second patterned circuit layer extending beyond a sidewall of the second through hole.